Abstract: A data storage circuit includes memory, an error correcting code (ECC) storage circuit, and control circuitry. The memory is configured to store a data value comprising a plurality of fields. Each of the fields is independently writable. The ECC storage circuit is configured to store an ECC value corresponding to the data value. The control circuitry is configured to receive a field value to be written into one of the fields, and store the field value in the one of the fields by writing only the field value to the memory. The control circuitry is also configured to retrieve the ECC value from the ECC storage circuit, compute an updated ECC value based on the ECC value retrieved from the ECC storage circuit and the field value, and store the updated ECC value in the ECC storage circuit.

Abstract: An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.

Abstract: In described examples, an SoC includes at least two voltage domains interconnected with a communication bus. Detection logic in a first voltage domain determines when a voltage error occurs in a second voltage domain and isolates communication via the communication bus when a voltage error or a timing error is detected.

Abstract: A synchronization circuit includes a first synchronizer having a first data input, a first clock input, and first output; a second synchronizer having a second data input, a second clock input, and a second output; selection circuitry having first, second, third and fourth inputs, and a synchronized data output, the first and second inputs coupled to the first and second outputs, respectively; and storage circuitry having a storage data input coupled to the synchronized data output, a third clock input, and a feedback output coupled to the fourth input.

Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.

Abstract: A system-on-chip includes first and second devices. An interconnect segment couples between the first and second devices. A bridge is coupled between the first and second devices and coupled to the interconnect segment. At least one of the bridge or interconnect segment include first and second multiplexers, a monitor circuit, and exclusive-OR logic. The first multiplexer has first and second multiplexer inputs and a first multiplexer output. The second multiplexer has third and fourth multiplexer inputs and a second multiplexer output. The monitor circuit has a first and second monitor circuit outputs. The first monitor circuit output is coupled to the second multiplexer input and the second monitor circuit output is coupled to the fourth multiplexer input. The exclusive-OR logic has first and second exclusive-OR logic inputs. The first exclusive-OR logic input couples to the first multiplexer output and the second exclusive-OR logic input couples to the second multiplexer output.

Abstract: A synchronization circuit includes a first synchronizer, a second synchronizer, and selection circuitry. The first synchronizer is configured to synchronize a received signal to a clock signal. The second synchronizer is disposed in parallel with the first synchronizer and configured to synchronize the received signal to the clock signal. The selection circuitry is coupled to the first synchronizer and the second synchronizer. The selection circuitry is configured to provide an output value generated by the first synchronizer at an output terminal of the synchronization circuit based on the output value generated by the first synchronizer being the same as an output value generated by the second synchronizer.

Abstract: Systems, methods and devices that improve fault detection capability of an imaging/vision hardware accelerator are provided. One such system includes a hardware accelerator, a signature generator, a signature processor, and a controller. These components cooperate to generate first and second output frames based on first and second reference frames, respectively; generate a third output frame based on a use-case frame; generate first and second image signatures based on the first and second output frames, respectively; compare the first image signature to a stored first reference image signature and output a first result; and compare the second image signature to a stored second reference image signature and output a second result. The controller determines, based on the results, whether the hardware accelerator has a fault at either a first time or a second time. When no fault is detected at either time, the controller analyzes the use-case frame for designation as an adaptive reference frame.

Abstract: In described examples, an SoC includes at least two voltage domains interconnected with a communication bus. Detection logic in a first voltage domain determines when a voltage error occurs in a second voltage domain and isolates communication via the communication bus when a voltage error or a timing error is detected.

Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.

Abstract: An electronic device may be configured to detect a fault in imaging and vision hardware accelerators. The electronic device may include a controller configured to select a first golden input frame of multiple golden input frames to perform a first self-test, and retrieve a first reference image signature corresponding to the first golden input frame. The electronic device may include a hardware accelerator module configured to obtain the first golden input frame, and generate a first output frame based on the first golden input frame. The electronic device may include a signature generator configured to generate a first generated image signature based on the first output frame. The electronic device may include a signature comparison module configured to compare the first generated image signature to the first reference image signature in order to determine whether the hardware accelerator module includes a fault at a first time.

Abstract: A data storage circuit includes memory, an error correcting code (ECC) storage circuit, and control circuitry. The memory is configured to store a data value comprising a plurality of fields. Each of the fields is independently writable. The ECC storage circuit is configured to store an ECC value corresponding to the data value. The control circuitry is configured to receive a field value to be written into one of the fields, and store the field value in the one of the fields by writing only the field value to the memory. The control circuitry is also configured to retrieve the ECC value from the ECC storage circuit, compute an updated ECC value based on the ECC value retrieved from the ECC storage circuit and the field value, and store the updated ECC value in the ECC storage circuit.

Abstract: An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.

Abstract: A data storage circuit includes memory, an error correcting code (ECC) storage circuit, and control circuitry. The memory is configured to store a data value comprising a plurality of fields. Each of the fields is independently writable. The ECC storage circuit is configured to store an ECC value corresponding to the data value. The control circuitry is configured to receive a field value to be written into one of the fields, and store the field value in the one of the fields by writing only the field value to the memory. The control circuitry is also configured to retrieve the ECC value from the ECC storage circuit, compute an updated ECC value based on the ECC value retrieved from the ECC storage circuit and the field value, and store the updated ECC value in the ECC storage circuit.

Abstract: An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.

Abstract: A synchronization circuit includes a first synchronizer, a second synchronizer, and selection circuitry. The first synchronizer is configured to synchronize a received signal to a clock signal. The second synchronizer is disposed in parallel with the first synchronizer and configured to synchronize the received signal to the clock signal. The selection circuitry is coupled to the first synchronizer and the second synchronizer. The selection circuitry is configured to provide an output value generated by the first synchronizer at an output terminal of the synchronization circuit based on the output value generated by the first synchronizer being the same as an output value generated by the second synchronizer.

Abstract: A synchronization circuit includes a first synchronizer, a second synchronizer, and selection circuitry. The first synchronizer is configured to synchronize a received signal to a clock signal. The second synchronizer is disposed in parallel with the first synchronizer and configured to synchronize the received signal to the clock signal. The selection circuitry is coupled to the first synchronizer and the second synchronizer. The selection circuitry is configured to provide an output value generated by the first synchronizer at an output terminal of the synchronization circuit based on the output value generated by the first synchronizer being the same as an output value generated by the second synchronizer.

Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.

Abstract: A system-on-chip includes first and second devices. An interconnect segment couples between the first and second devices. A bridge is coupled between the first and second devices and coupled to the interconnect segment. At least one of the bridge or interconnect segment include first and second multiplexers, a monitor circuit, and exclusive-OR logic. The first multiplexer has first and second multiplexer inputs and a first multiplexer output. The second multiplexer has third and fourth multiplexer inputs and a second multiplexer output. The monitor circuit has a first and second monitor circuit outputs. The first monitor circuit output is coupled to the second multiplexer input and the second monitor circuit output is coupled to the fourth multiplexer input. The exclusive-OR logic has first and second exclusive-OR logic inputs. The first exclusive-OR logic input couples to the first multiplexer output and the second exclusive-OR logic input couples to the second multiplexer output.

Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.