Abstract: A circuit arrangement includes a reduction operator circuits arranged in a first level of a reduction tree. Each reduction operator circuit accumulates respective products into a respective sum. Quantizer circuits are configured to quantize the sums from the reduction operator circuits into quantized sums, respectively, based on values of the sums relative to respective first thresholds. Another reduction operator circuit is arranged in a second level of the reduction tree and is configured to accumulate the quantized sums and provide a first sum. A second-level quantizer circuit is configured to quantize the first sum into a quantized first sum based on a value of the first sum relative to a second threshold.

Abstract: An adder for fractional logarithmic number system (FLNS) format operands includes a compare-and-swap circuit that inputs first and second FLNS operands represented by fixed point values and provides a greater one as operand x and a lesser or equal one as operand y. Sign bits are sx and sy of x and y, respectively, qx and qy, are integer portions of x and y, respectively, fraction portions of x and y have integer values rx and ry, respectively. The compare-and-swap circuit is configured to provide sx as a sign bit, sz of a sum z=x(1+y/x) for x?0. A subtraction circuit subtracts (qy+ry/n)?(qx+rx/n) and outputs q? and r?, such that ?=y/x, where n=2wr and wr is a bit-width of rx and ry. An approximation circuit provides an approximation of (1+?) to a nearest FLNS value, ?, as fixed point value having an integer portion q? and a fraction portion that has an integer value r?.