Abstract: Integrated circuits and methods of forming integrated circuits are provided. A method of forming an integrated circuit includes providing a substrate that includes an electrical contact disposed therein. A first dielectric layer is formed over the substrate and electrical contact. A metal-containing layer is patterned over the first dielectric layer, with at least a first portion of the patterned metal-containing layer disposed over the first dielectric layer. The patterned metal-containing layer is absent in regions of the first dielectric layer over the electrical contact. A second dielectric layer is formed over the patterned metal-containing layer. A first via is etched in the first dielectric layer and the second dielectric layer over the electrical contact, and a second via is etched in the second dielectric layer over the patterned metal-containing layer. The first via and the second via are filled with an electrically-conductive material.

Abstract: Integrated circuits and methods of forming integrated circuits are provided. A method of forming an integrated circuit includes providing a substrate that includes an electrical contact disposed therein. A first dielectric layer is formed over the substrate and electrical contact. A metal-containing layer is patterned over the first dielectric layer, with at least a first portion of the patterned metal-containing layer disposed over the first dielectric layer. The patterned metal-containing layer is absent in regions of the first dielectric layer over the electrical contact. A second dielectric layer is formed over the patterned metal-containing layer. A first via is etched in the first dielectric layer and the second dielectric layer over the electrical contact, and a second via is etched in the second dielectric layer over the patterned metal-containing layer. The first via and the second via are filled with an electrically-conductive material.

Abstract: A method of forming a barrier layer and cap comprised of CuSiN for an interconnect. We provide an interconnect opening in a dielectric layer over a semiconductor structure. We form a CuSiN barrier layer over the sidewalls and bottom of the interconnect opening by reacting with the first copper layer. We then form an interconnect over the CuSiN layer filling the interconnect opening. We can form a CuSiN cap layer on the top surface of the interconnect.

Abstract: A method of sputtering a Ta layer comprised of alpha phase Ta on a Cu layer. An embodiment includes a Ta sputter deposition on a Cu surface at a substrate temperature less than 200° C. Another embodiment has a pre-cooling step at a temperature less than 100° C. prior to Ta layer sputter deposition. In another non-limiting example embodiment, a pre-clean step comprising an inert gas sputter is performed prior to the tantalum sputter. Another non-limiting example embodiment provides a semiconductor structure comprising: a semiconductor structure; a copper layer over the semiconductor structure; a tantalum layer on the copper layer; the tantalum layer comprised alpha phase Ta; a metal layer on the tantalum layer.

Abstract: A method of sputtering a Ta layer comprised of alpha phase Ta on a Cu layer. An embodiment includes a Ta sputter deposition on a Cu surface at a substrate temperature less than 200° C. Another embodiment has a pre-cooling step at a temperature less than 100° C. prior to Ta layer sputter deposition. In another non-limiting example embodiment, a pre-clean step comprising an inert gas sputter is performed prior to the tantalum sputter. Another non-limiting example embodiment provides a semiconductor structure comprising: a semiconductor structure; a copper layer over the semiconductor structure; a tantalum layer on the copper layer; the tantalum layer comprised alpha phase Ta; a metal layer on the tantalum layer.