Abstract: One embodiment of the present invention provides a method of manufacturing an electronic device using a cyclic doping process including i) an operation of forming a unit transfer thin film including a two-dimensional material on a transfer substrate, ii) an operation of doping the unit transfer thin film in a low-damage doping process, iii) an operation of transferring the unit transfer thin film doped according to the operation ii) on a transfer target substrate, and iv) an operation of repeatedly performing the operations i) to iii) several times to reach a target thickness.

Abstract: A method creates a training data set for optical railway detection with integrated obstacle detection. The method includes the following steps of: providing first images of railways for rail vehicles, each first image having a representation of a railway; providing second images of objects, each second image containing a representation of at least one object; combining the first and second images; and generating third images containing the combined first and second images. Each third image contains a representation of a railway with at least one object, and a number of the third images forming the training data set for the optical railway detection with integrated obstacle detection.

Abstract: A solar cell testing system including a lower electrode, a solar cell, an encapsulation material, a sodium-containing template, an upper electrode, a voltage source and a measuring circuit is provided. The solar cell is disposed on the lower electrode. The encapsulation material is disposed on the solar cell. The sodium-containing template is disposed on the encapsulation material, wherein the sodium-containing template has a sodium ion content ranging between 9-39%. The upper electrode is disposed on the sodium-containing template. The voltage source is connected between the upper electrode and the lower electrode. The measuring circuit is connected between the solar cell and the lower electrode for measuring a shunt resistance of the solar cell.

Abstract: A solar cell testing system including a lower electrode, a solar cell, an encapsulation material, a sodium-containing template, an upper electrode, a voltage source and a measuring circuit is provided. The solar cell is disposed on the lower electrode. The encapsulation material is disposed on the solar cell. The sodium-containing template is disposed on the encapsulation material, wherein the sodium-containing template has a sodium ion content ranging between 9-39%. The upper electrode is disposed on the sodium-containing template. The voltage source is connected between the upper electrode and the lower electrode. The measuring circuit is connected between the solar cell and the lower electrode for measuring a shunt resistance of the solar cell.

Abstract: A programmable-threshold power supply selector has two power-supply inputs VDD1 and VDD2. The higher of these two voltages is pre-selected as a common supply that powers all transistors and circuitry in the programmable-threshold power supply selector, including substrates under transistors. An open-loop decision circuit is very stable since it uses no feedback. A tunable voltage divider divides VDD1 by a programmable divisor. The divided VDD1 is compared to a reference voltage to generate switch-control signals. The switch-control signals drive the gates of p-channel switch transistors that connect either VDD1 or VDD2 to an output supply voltage. The different programmable divisor values effectively cause VDD1 to be compared to a programmable threshold voltage VTH. The switch transistors switch the output supply voltage to VDD2 only when VDD1 falls below VTH. The output supply voltage remains at VDD1 even when VDD1 falls below VDD2, eliminating unnecessary power switching.

Abstract: An integrator in a duty-cycle adjustment circuit has an adjustable charging current provided by a switched current-source array in response to configuration signals from the calibration logic. The integrator's ramp voltage is compared to a threshold voltage by a comparator to generate an output clock. A tunable voltage reference generates a reference voltage that can be tuned by configuration signals from the calibration logic. The reference voltage is divided by a tunable voltage divider, which selects different fractions of the reference voltage for use as the threshold voltage. During calibration, calibration logic repeatedly raises the reference voltage or reduces the charging current from the switched current-source array until a peak voltage of the ramp voltage equals the reference voltage, when a zero duty onset detector detects that the output clock has stopped pulsing. The configuration signals at the zero duty onset condition are stored and used for normal operation.

Abstract: A programmable-threshold power supply selector has two power-supply inputs VDD1 and VDD2. The higher of these two voltages is pre-selected as a common supply that powers all transistors and circuitry in the programmable-threshold power supply selector, including substrates under transistors. An open-loop decision circuit is very stable since it uses no feedback. A tunable voltage divider divides VDD1 by a programmable divisor. The divided VDD1 is compared to a reference voltage to generate switch-control signals. The switch-control signals drive the gates of p-channel switch transistors that connect either VDD1 or VDD2 to an output supply voltage. The different programmable divisor values effectively cause VDD1 to be compared to a programmable threshold voltage VTH. The switch transistors switch the output supply voltage to VDD2 only when VDD1 falls below VTH. The output supply voltage remains at VDD1 even when VDD1 falls below VDD2, eliminating unnecessary power switching.

Abstract: A photovoltaic device includes a substrate, a transparent conductive oxide, an n-type window layer, a p-type absorber layer and an electron reflector layer. The electron reflector layer may include zinc telluride doped with copper telluride, zinc telluride alloyed with copper telluride, or a bilayer of multiple layers containing zinc, copper, cadmium and tellurium in various compositions. A process for manufacturing a photovoltaic device includes forming a layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process includes forming an electron reflector layer over a p-type absorber layer.

Abstract: A method to improve CdTe-based photovoltaic device efficiency is disclosed, the method including steps for removing surface contaminants from a semiconductor absorber layer prior to the deposition or formation of a back contact layer on the semiconductor absorber layer, the surface contaminants removed using at least one of a dry etching process and a wet etching process.

Abstract: A method to improve operation of a CdTe-based photovoltaic device is disclosed, the method comprising the steps of depositing a semiconductor absorber layer adjacent to a substrate, depositing a semiconductor buffer layer adjacent to the semiconductor layer, and annealing at least one of the semiconductor absorber layer and the semiconductor buffer layer with one of a laser and a flash lamp.

Abstract: A photovoltaic device includes a substrate, a transparent conductive oxide, an n-type window layer, a p-type absorber layer and an electron reflector layer. The electron reflector layer may include zinc telluride doped with copper telluride, zinc telluride alloyed with copper telluride, or a bilayer of multiple layers containing zinc, copper, cadmium and tellurium in various compositions. A process for manufacturing a photovoltaic device includes forming a layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process includes forming an electron reflector layer over a p-type absorber layer.

Abstract: A photovoltaic device includes a substrate, a transparent conductive oxide, an n-type window layer, a p-type absorber layer and an electron reflector layer. The electron reflector layer may include zinc telluride doped with copper telluride, zinc telluride alloyed with copper telluride, or a bilayer of multiple layers containing zinc, copper, cadmium and tellurium in various compositions. A process for manufacturing a photovoltaic device includes forming a layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process includes forming an electron reflector layer over a p-type absorber layer.

Abstract: A method to improve operation of a CdTe-based photovoltaic device is disclosed, the method comprising the steps of depositing a semiconductor absorber layer adjacent to a substrate, depositing a semiconductor buffer layer adjacent to the semiconductor layer, and annealing at least one of the semiconductor absorber layer and the semiconductor buffer layer with one of a laser and a flash lamp.

Abstract: A photovoltaic device includes a substrate, a transparent conductive oxide, an n-type window layer, a p-type absorber layer and an electron reflector layer. The electron reflector layer may include zinc telluride doped with copper telluride, zinc telluride alloyed with copper telluride, or a bilayer of multiple layers containing zinc, copper, cadmium and tellurium in various compositions. A process for manufacturing a photovoltaic device includes forming a layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process includes forming an electron reflector layer over a p-type absorber layer.

Abstract: A back electrode for a PV device and method of formation are disclosed. A ZnTe material is provided over an absorber material and a MoNx material is provided over the ZnTe material. A Mo material may also be included in the back electrode above or below the MoNx layer and a metal layer may be also provided over the MoNx layer.

Abstract: A method to improve CdTe-based photovoltaic device efficiency is disclosed, the method including steps for removing surface contaminants from a semiconductor absorber layer prior to the deposition or formation of a back contact layer on the semiconductor absorber layer, the surface contaminants removed using at least one of a dry etching process and a wet etching process.

Abstract: A method of LED manufacturing is disclosed. A coating is applied to a mesa. This coating may have different thicknesses on the sidewalls of the mesa compared to the top of the mesa. Ion implantation into the mesa will form implanted regions in the sidewalls in one embodiment. These implanted regions may be used for LED isolation or passivation.

Abstract: An improved method of creating LED arrays is disclosed. A p-type layer, multi-quantum well and n-type layer are disposed on a substrate. The device is then etched to expose portions of the n-type layer. To create the necessary electrical isolation between adjacent LEDs, an ion implantation is performed to create a non-conductive implanted region. In some embodiments, an implanted region extends through the p-type layer, MQW and n-type layer. In another embodiment, a first implanted region is created in the n-type layer. In addition, a second implanted region is created in the p-type layer and multi-quantum well immediately adjacent to etched n-type layer. In some embodiments, the ion implantation is done perpendicular to the substrate. In other embodiments, the implant is performed at an angle.

Abstract: An improved method of fabricating a vertical semiconductor LED is disclosed. Ions are implanted into the LED to create non-conductive regions, which facilitates current spreading in the device. In some embodiments, the non-conductive regions are located in the p-type layer. In other embodiments, the non-conductive layer may be in the multi-quantum well or n-type layer.