Patents by Inventor Sandeep B V

Sandeep B V has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Flip-flop with single pre-charge node
    Patent number: 10715118
    Abstract: Various example embodiments herein disclose a flip-flop including a master latch comprising one of: a plurality of P-type metal-oxide-semiconductor (PMOS) and a plurality of N-type metal-oxide-semiconductor (NMOS). A slave latch includes one of: a plurality of PMOS and a plurality of NMOS. An inverted clock signal input is communicatively connected with the master latch and the slave latch. The master latch includes a single pre-charge node. The single pre-charge node sets up a data capture path in the flip flop. Data is stored in the master latch and the slave latch via the pre-charge node.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shyam Agarwal, Sandeep B V, Shreyas Samraksh Jayaprakash, Abhishek Kumar Ghosh, Parvinder Kumar Rana
  • D FLIP-FLOPS WITH LOW CLOCK DISSIPATION POWER
    Publication number: 20200044631
    Abstract: A D flip-flop includes a master block configured to latch an input value of D at one of rising edge and a falling edge of a clock signal, based on the clock signal, the input value of D, and an inverted value of D, and a slave block configured to propagate the input value of D at another one of the falling edge and the rising edge of the clock signal, based on the clock signal.
    Type: Application
    Filed: October 5, 2018
    Publication date: February 6, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shyam AGARWAL, Sandeep B V, Sheetal Y KOCHREKAR, Abhishek GHOSH, Parvinder Kumar RANA, Rohit BISHT
  • FLIP-FLOP WITH SINGLE PRE-CHARGE NODE
    Publication number: 20190058461
    Abstract: Various example embodiments herein disclose a flip-flop including a master latch comprising one of: a plurality of P-type metal-oxide-semiconductor (PMOS) and a plurality of N-type metal-oxide-semiconductor (NMOS). A slave latch includes one of: a plurality of PMOS and a plurality of NMOS. An inverted clock signal input is communicatively connected with the master latch and the slave latch. The master latch includes a single pre-charge node. The single pre-charge node sets up a data capture path in the flip flop. Data is stored in the master latch and the slave latch via the pre-charge node.
    Type: Application
    Filed: August 13, 2018
    Publication date: February 21, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Shyam AGARWAL, Sandeep B V, Shreyas Samraksh Jayaprakash, Abhishek Kumar Ghosh, Parvinder Kumar Rana