Abstract: A circuit arrangement includes an array of switches that represent a Boolean satisfiability expression that has a plurality of clauses each defined by a combination of Boolean variables Xi or ¬Xi, a first plane, and a constraints network operatively arranged with the first plane. The constraints network enforces each of the clauses such that values of different ones of the variables continue to randomly or pseudo randomly flip until the values of the variables Xi and ¬Xi stop changing or a predetermined condition occurs.

Abstract: A system and associated methods for accurate localization of seizure onset zone (SOZ) from independent components (IC) of resting state functional magnetic resonance imaging (rs-fMRI) to improve surgical outcomes in children with Drug Resistant Epilepsy (DRE) are disclosed. The system and methods define a phased approach, where fMRI noise-related biomarkers are used through high fidelity image processing techniques to eliminate noise ICs. Then SOZ markers are used through a maximum likelihood-based classifier to determine SOZ localizing ICs.

Abstract: Disclosed are various embodiments for data anomaly detection. A variable profile is generated for each variable in source data. Then, the variable profiles are provided to each of a plurality of machine learning models. Next, it is determined, with each of the plurality of machine learning models, whether each variable profile is anomalous. The determination, from each of the plurality of machine learning models, whether each variable profile is anomalous is provided to an ensemble model. The ensemble model then generates a final determination whether each variable profile is anomalous. The final determination is then reported to an analysis service.

Abstract: A system and method of automated driver selection is disclosed. A plurality of driver profiles and a first order are received. Each of the driver profiles includes at least one driver parameter. The first order includes at least one order parameter. A driver score is calculated for each of the plurality of driver profiles for the first order. The driver score is calculated based on the at least one driver parameter and the at least one order parameter. Each driver profile is ranked based on the calculated driver score and a first delivery assignment request is transmitted to a system associated with a first-ranked driver profile. A response is received to the first delivery assignment request.

Abstract: A display may be formed by an array of light-emitting diodes mounted to the surface of a display substrate. The light-emitting diodes may be inorganic light-emitting diodes formed from separate crystalline semiconductor structures. An array of pixel control circuits may be used to control light emission from the light-emitting diodes. Each pixel control circuit may be configured to control one or more respective passive matrices. To control partial pixel cells in the display, a donor pixel control circuit in a partial pixel cell may control the pixels in a receptor partial pixel cell without a pixel control circuit. To mitigate the size of an inactive area of the display, fanout signal lines for the display may be formed in the light-emitting active area of the display. The fanout signal lines may be formed between a row of pixel control circuits and a bottom edge of the light-emitting active area.

Abstract: A phase-locked loop (PLL) is implemented to have another (second) PLL in place of the controlled oscillator. When a known frequency change in the frequency of the output clock is desired, in addition to changing a configuration of the PLL (first PLL), the configuration of the second PLL is also changed to cause the frequency of the output clock to change quickly. In various embodiments, the configuration of the second PLL is changed by changing the divisor of the feedback divider of the second PLL, the divisor in a pre-scaler in the second PLL, the control voltage of a VCO used in the second PLL, and any other point of user control in the second PLL.

Abstract: A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates, retaining the critical cache lines with a certain probability when victim cache blocks are being selected, etc. Criticality values may be retained at various levels of the cache hierarchy. Additionally, accelerated eviction may be employed if the threads previously accessing the critical cache blocks are viewed as dead.

Abstract: A method for a process of signal transmission between a plurality of electrical units, wherein the method comprises: electrically interconnecting the plurality of electrical units by way of a plurality of electrical junction blocks, each electrical junction block of the plurality of electrical junction blocks comprising one or more terminals. An arrangement for signal transmission between a plurality of electrical units, wherein the arrangement comprises a plurality of electrical junction blocks for electrically interconnecting the plurality of electrical units, and wherein each electrical junction block of the plurality of electrical junction blocks comprises one or more terminals.

Abstract: A variable latency cache memory is disclosed. A cache subsystem includes a pipeline control circuit configured to initiate cache memory accesses for data. The cache subsystem further includes a cache memory circuit having a data array arranged into a plurality of groups, wherein different ones of the plurality of groups have different minimum access latencies due to different distances from the pipeline control circuit. A plurality of latency control circuits configured to ensure a latency is bounded to a maximum value for a given access to the data array, wherein a given latency control circuit is associated with a corresponding group of the plurality of groups. The latency for a given access may thus vary between a minimum access latency for a group closest to the pipeline control circuit to a maximum latency for an access to the group furthest from the pipeline control circuit.

Abstract: An apparatus includes a plurality of processor circuits, a cache memory circuit, and a trace control circuit. The trace control circuit may be configured, in response to activation of a mode to record information indicative of program execution of at least one processor circuit of the plurality of processor circuits, to monitor memory requests transmitted between ones of the plurality of processor circuits and the cache memory circuit, and then to select a particular memory request of monitored memory requests using an arbitration algorithm. The trace control circuit may be further configured to allocate space in a trace buffer to the particular memory request, and to store, in the trace buffer, information associated with the particular memory request.

Abstract: The operational characteristics of a cyber-physical system (CPS) may deviate from the certified system due to intended (in case of cheating) or unintended (wear and tear) reasons. A computer-implemented certification system makes test case search aware of the multidimensional interactions between the cyber and physical subsystems and addresses practical dynamical system problems like Zeno behavior and dynamical model divergence. The system dynamically modulates an input search space by predicting and limiting input variations that can potentially cause divergence or Zeno behavior.

Abstract: A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates, retaining the critical cache lines with a certain probability when victim cache blocks are being selected, etc. Criticality values may be retained at various levels of the cache hierarchy. Additionally, accelerated eviction may be employed if the threads previously accessing the critical cache blocks are viewed as dead.

Abstract: A cache may include multiple request handling pipes, each of which may further include multiple request buffers, for storing device requests from one or more processors to one or more devices. Some of the device requests may require to be sent to the devices according to an order. For a given one of such device requests, the cache may select a request handling pipe, based on an address indicated by the device request, and select a request buffer, based on the available entries of the request buffers of the selected request handling pipe, to store the device request. The cache may further use a first-level and a second-level token stores to track and maintain the device requests in order when transmitting the device requests to the devices.

Abstract: A system and associated methods/processes includes a sensor operable to capture sensor data indicative of a gesture; and a processor in communication with a memory and the sensor. The processor is configured to execute instructions stored in the memory, which, when executed, cause the processor to access the sensor data and decompose the gesture into a canonical gesture form defining a string of gesture components arranged in a spatio-temporal order.

Abstract: Embodiments of the disclosure relate generally to formulations, methods of treatment, kits, and dosage forms for treating inflammatory disorders, including topic dermatitis, cancer, the formulations comprising an active pharmaceutical ingredient. The formulation provided comprises granules, wherein the granules comprise: micronized active ingredient; one or more granulation binders; one or more fillers; one or more disintegrants; and one or more antioxidants. In one embodiment, the methods of treatment include orally administering the active ingredient to a subject suffering from atopic dermatitis, where the active ingredient, is in an amount of about 20 mg to about 80 mg.

Abstract: An apparatus includes a plurality of processor circuits, a cache memory circuit, and a trace control circuit. The trace control circuit may be configured, in response to activation of a mode to record information indicative of program execution of at least one processor circuit of the plurality of processor circuits, to monitor memory requests transmitted between ones of the plurality of processor circuits and the cache memory circuit, and then to select a particular memory request of monitored memory requests using an arbitration algorithm. The trace control circuit may be further configured to allocate space in a trace buffer to the particular memory request, and to store, in the trace buffer, information associated with the particular memory request.

Abstract: A cache may include multiple request handling pipes, each of which may further include multiple request buffers, for storing device requests from one or more processors to one or more devices. Some of the device requests may require to be sent to the devices according to an order. For a given one of such device requests, the cache may select a request handling pipe, based on an address indicated by the device request, and select a request buffer, based on the available entries of the request buffers of the selected request handling pipe, to store the device request. The cache may further use a first-level and a second-level token stores to track and maintain the device requests in order when transmitting the device requests to the devices.

Abstract: Systems and methods for generating a custom document template are disclosed. An example method may be performed by one or more processors of a system and include retrieving a user document including a user data entry in a user data field, identifying a set of system data fields within a plurality of system documents potentially relevant to the user document, determining, for each of the set of system data fields, a weighted value indicative of a likelihood that the system data field is relevant to the user data field, identifying a most relevant system data field of the set of system data fields, the most relevant system data field having a highest weighted value of the determined weighted values, and generating a custom document template including a dynamic data region for the user data entry, the dynamic data region mapped to the most relevant system data field.

Abstract: Distributed firewalls in a network are disclosed. Example firewall controllers disclosed herein are to instruct a first network node of a software-defined network to implement a first firewall instance of a distributed firewall, the first network node to implement the first firewall instance with a first virtual machine. Disclosed example firewall controllers are also to configure a second network node of the software-defined network to route network traffic through the first firewall instance and, after at least some of the network traffic is dropped by the first firewall instance, instruct the second network node to implement a second firewall instance of the distributed firewall, the second network node to implement the second firewall instance with a second virtual machine.

Abstract: Calculating energy loss during an outage, including: determining that windspeed data indicating device windspeeds measured at an energy generating device are unavailable within a particular time duration; receiving meteorological data associated with a site location of the energy generating device, the meteorological data including meteorological windspeed data collected within the particular time duration; and predicting one or more estimated device windspeeds at the energy generating device during the particular time duration based on the meteorological data using a trained model for the energy generating device, the trained model being trained using a machine learning algorithm that utilizes historical meteorological windspeed data associated with the site location collected during a previous time duration and corresponding historical device windspeed data measured at the energy generating device during the previous time duration.