Abstract: Embodiments for methods, systems and apparatuses for improving brokerage transactions through a server are disclosed. In one aspect, the method includes receiving, input by a user, relevant data, storing the relevant data in a database, and identifying a plurality of agents from a list of agents by using the relevant data. The method further includes receiving at least two bids associated with at least one agent of the identified plurality of agents, and each bid includes at least one of: commission charged to user or commission rebate to user. The method further includes providing the at least two bids associated with the at least one of the identified plurality of agents to the user.

Abstract: Disclosed are methods and devices to provide a transaction over a network. In one embodiment, a machine-implemented method includes: opening, through an enclave device, an in-band channel or an out-of-band channel over the network; authenticating, through the enclave device, a user of a resource over the in-band channel or the out-of-band channel; facilitating, through the enclave device, an authorization of the user to access the resource over the in-band channel or the out-of-band channel; and accounting for a transaction conducted by the user accessing the resource, through the enclave device, over the in-band channel or the out-of-band channel.

Abstract: Disclosed are methods, devices, and systems to provide an end-to-end secure transaction over a network. In one embodiment, a machine-implemented method comprises opening an in-band channel or an out-of-band channel over the network; authenticating, through the control plane of a switch managing the network, a user of a resource over the in-band channel or the out-of-band channel; authorizing the user, through the control plane, access to the resource over the in-band channel or the out-of-band channel; and accounting for a transaction conducted by the user accessing the resource, through the control plane, over the in-band channel or the out-of-band channel. In another embodiment, a switch to manage the network and to implement the method described herein is disclosed.

Abstract: Disclosed are methods, devices, and systems to provide an end-to-end secure transaction over a software defined network (SDN). In one embodiment, a machine-implemented method comprises opening an in-band virtual secure channel (VSC) or an out-of-band VSC over the SDN; authenticating, through the control plane of a switch managing the SDN, a user of a resource over the in-band VSC or the out-of-band VSC; authorizing the user, through the control plane, access to the resource over the in-band VSC or the out-of-band VSC; and accounting for a transaction conducted by the user accessing the resource, through the control plane, over the in-band VSC or the out-of-band VSC. In another embodiment, a switch to manage the SDN and to implement the method described herein is disclosed.

Abstract: Disclosed are methods and devices to provide an end-to-end secure transaction over a software defined network (SDN). In one embodiment, a machine-implemented method includes: opening, through an enclave device, an in-band virtual secure channel (VSC) or an out-of-band VSC over the SDN; authenticating, through the enclave device, a user of a resource over the in-band VSC or the out-of-band VSC; facilitating, through the enclave device, an authorization of the user to access the resource over the in-band VSC or the out-of-band VSC; and accounting for a transaction conducted by the user accessing the resource, through the enclave device, over the in-band VSC or the out-of-band VSC.

Abstract: Embodiments of the invention provide a method of authenticating a physical document, comprising obtaining an electronic representation of at least part of the physical document; extracting at least one error detection code from the electronic representation; and using the at least one error detection code to detect errors in image data within the electronic representation. Embodiments of the invention also provide a method of securing a physical document, comprising obtaining an electronic representation of at least part of the physical document; determining at least one error detection code for image data within the electronic representation; and producing a secure physical document comprising the electronic representation and a machine readable marking including the at least one error detection code.

Abstract: In a high order delta sigma modulator stage having integrators with pipelined cross coupled input circuits, the processing delay between an upstream integrator and a downstream integrator is decreased from a full cycle of a clock used to control the high order delta sigma modulator stage to a half cycle of the clock, while the processing delay between a quantizer and a portion of a digital-to-analog converter that provides feedback to the upstream integrator is increased by a half cycle of the clock.

Abstract: A system reduces unwanted oscillations in a multiple gigabit per second, high gain amplifier portion. The system includes a power source portion having a plurality of power sources and a bias current portion having a plurality of bias current devices. The system also includes an amplification portion having a plurality of amplifiers. A first group of the plurality of amplifiers is coupled to the power source portion and the bias current portion, such that feedback voltage is substantially eliminated to substantially eliminate oscillations in the amplification portion.

Abstract: The present invention relates to a replica network for linearizing switched capacitor circuits. A bridge circuit with a MOSFET resistor disposed in a resistor branch of the bridge circuit is provided. A noninverting terminal of an operational amplifier is connected to a first node of the bridge circuit and an inverting terminal of the operational amplifier is connected to a second node of the bridge circuit. The second node is separated from the first node by another node of the bridge circuit. An output of the operational amplifier is provided to a gate terminal of the MOSFET resistor and to the gate terminal of the MOSFET switch in a switched capacitor circuit, thereby controlling the resistance of the MOSFET switch so that it is independent of the signal voltage. In this manner, the replica network of the present invention linearizes the switched capacitor circuit. In this manner, the replica network of the present invention linearizes the switched capacitor circuit.

Abstract: A biasing scheme for a MOSFET that mitigates the MOSFET body effect. The biasing scheme can be realized replicating the voltage at the source terminal of a MOSFET and applying this replicated voltage to the body terminal. In this manner, the effect of the body transconductance, at high frequencies, becomes a function of the ratio of the well-to-substrate capacitance of the MOSFET to the sum of the well-to-substrate capacitance and the source-to-body capacitance of the transistor. At high frequencies, the biasing scheme mitigates the reduction in gain of a source follower caused by the body effect of a driven MOSFET within the source follower, improves the stability of a feedback network established by a gain boosting amplifier and the driven MOSFET by contributing a negative half plane zero to the transfer function of the feedback network, and reduces the power consumed by the gain boosting amplifier.

Abstract: A system for receiving signals (e.g., optical signals) includes an input device, an amplification device, and a feedback device. The amplification device receives a signal from the input device and includes a transimpedance portion. The transimpedance portion includes a first section having a plurality of elements (e.g., resistors and transistors) and a second section having a plurality of elements (e.g., resistors and transistors). One or more of the elements (e.g. transistors or resistors) in the first and second sections are mismatched to introduce a systematic offset in the transimpedance stage, to make the net input referred offset of the amplification device unidirectional. The feedback device (e.g. an integrator) is coupled to an output of the amplification device and an input of the transimpedance portion to provide a unidirectional offset correction to the amplification device for reduced noise enhancement.

Abstract: A biasing scheme for a MOSFET that mitigates the MOSFET body effect. The biasing scheme can be realized replicating the voltage at the source terminal of a MOSFET and applying this replicated voltage to the body terminal. In this manner, the effect of the body transconductance, at high frequencies, becomes a function of the ratio of the well-to-substrate capacitance of the MOSFET to the sum of the well-to-substrate capacitance and the source-to-body capacitance of the transistor. At high frequencies, the biasing scheme mitigates the reduction in gain of a source follower caused by the body effect of a driven MOSFET within the source follower, improves the stability of a feedback network established by a gain boosting amplifier and the driven MOSFET by contributing a negative half plane zero to the transfer function of the feedback network, and reduces the power consumed by the gain boosting amplifier.

Abstract: In a high order delta sigma modulator stage having integrators with pipelined cross coupled input circuits, the processing delay between an upstream integrator and a downstream integrator is decreased from a full cycle of a clock used to control the high order delta sigma modulator stage to a half cycle of the clock, while the processing delay between a quantizer and a portion of a digital-to-analog converter that provides feedback to the upstream integrator is increased by a half cycle of the clock.

Abstract: A system reduces unwanted oscillations in a multiple gigabit per second, high gain amplifier portion. The system includes a power source portion having a plurality of power sources and a bias current portion having a plurality of bias current devices. The system also includes an amplification portion having a plurality of amplifiers. A first group of the plurality of amplifiers is coupled to the power source portion and the bias current portion, such that feedback voltage is substantially eliminated to substantially eliminate oscillations in the amplification portion.

Abstract: A system for receiving signals (e.g., optical signals) includes an input device, an amplification device, and a feedback device. The amplification device receives a signal from the input device and includes a transimpedance portion. The transimpedance portion includes a first section having a plurality of elements (e.g., resistors and transistors) and a second section having a plurality of elements (e.g., resistors and transistors). One or more of the elements (e.g. transistors or resistors) in the first and second sections are mismatched to introduce a systematic offset in the transimpedance stage, to make the net input referred offset of the amplification device unidirectional. The feedback device (e.g. an integrator) is coupled to an output of the amplification device and an input of the transimpedance portion to provide a unidirectional offset correction to the amplification device for reduced noise enhancement.

Abstract: A switched capacitor circuit having an integrator, a switch, a capacitor, a field effect transistor, and a network. The switch is connected to the integrator. The capacitor is connected to the switch. The field effect transistor is connected to the capacitor. The network is connected to a gate terminal of the field effect transistor. The network is configured to control a resistance of the field effect transistor in response to variations in an input signal voltage received at the field effect transistor.

Abstract: A system reduces unwanted oscillations in a multiple gigabit per second, high gain amplifier portion. The system includes a power source portion having a pluraty of power sources and a bias current portion having a pluraty of bias current devices. The system also includes an amplification portion having a plurality of amplifiers. A first group of the plurality of amplifiers is coupled to the power source portion and the bias current portion, such that feedback voltage is substantially eliminated to substantially eliminate oscillations in the amplification portion.

Abstract: A system reduces unwanted oscillations in a multiple gigabit per second, high gain amplifier portion. The system includes a power source portion having a plurality of power sources and a bias current portion having a plurality of bias current devices. The system also includes an amplification portion having a plurality of amplifiers. A first group of the plurality of amplifiers is coupled to the power source portion and the bias current portion, such that feedback voltage is substantially eliminated to substantially eliminate oscillations in the amplification portion.

Abstract: A method and apparatus enables echo reduction in a full duplex transceiver system. A replica current is subtracted from a receiver via a first differential circuit path that adaptively matches a time constant associated with a second differential circuit path that connects the receiver with an external data line.

Abstract: In a high order delta sigma modulator stage having integrators with pipelined cross coupled input circuits, the processing delay between an upstream integrator and a downstream integrator is decreased from a full cycle of a clock used to control the high order delta sigma modulator stage to a half cycle of the clock, while the processing delay between a quantizer and a portion of a digital-to-analog converter that provides feedback to the upstream integrator is increased by a half cycle of the clock.