Patents by Inventor Sandeep K. Jain
Sandeep K. Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10783397Abstract: Methods, systems, and storage media for image thresholding at a network edge device are disclosed herein. In an embodiment, a network edge device may include a camera to be operated by at least one of the one or more processors to capture a monitoring image of a condition proximal to the device at a location. An image threshold module may be operated by at least one of the one or more processors to determine if the monitoring image exceeds a threshold relating to the condition at the location. A communication module may communicate to a remote network location an indication if the monitoring image exceeds the threshold relating to the condition.Type: GrantFiled: June 29, 2016Date of Patent: September 22, 2020Assignee: Intel CorporationInventor: Sandeep K. Jain
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Patent number: 10070598Abstract: An agricultural data collection system may include a plurality of self-powered agricultural data collection devices disposed across an agricultural area. The agricultural data collection system may also include a plurality of self-powered agricultural output devices that control the distribution of one or more agricultural resources across at least a portion of the agricultural area. The plurality of self-powered agricultural data collection devices and the plurality of self-powered agricultural output devices may communicate wirelessly to selectively implement an agricultural management method that uses data collected by the self-powered agricultural data collection devices to provide agricultural resources where needed within localized agricultural areas within a larger agricultural area. At times, the agricultural management method may include an adaptive method that employs machine learning principles to optimize agricultural production within the agricultural area.Type: GrantFiled: December 24, 2015Date of Patent: September 11, 2018Assignee: Intel CorporationInventor: Sandeep K. Jain
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Publication number: 20180005076Abstract: Methods, systems, and storage media for image thresholding at a network edge device are disclosed herein. In an embodiment, a network edge device may include a camera to be operated by at least one of the one or more processors to capture a monitoring image of a condition proximal to the device at a location. An image threshold module may be operated by at least one of the one or more processors to determine if the monitoring image exceeds a threshold relating to the condition at the location. A communication module may communicate to a remote network location an indication if the monitoring image exceeds the threshold relating to the condition.Type: ApplicationFiled: June 29, 2016Publication date: January 4, 2018Inventor: SANDEEP K. JAIN
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Publication number: 20170181389Abstract: An agricultural data collection system may include a plurality of self-powered agricultural data collection devices disposed across an agricultural area. The agricultural data collection system may also include a plurality of self-powered agricultural output devices that control the distribution of one or more agricultural resources across at least a portion of the agricultural area. The plurality of self-powered agricultural data collection devices and the plurality of self-powered agricultural output devices may communicate wirelessly to selectively implement an agricultural management method that uses data collected by the self-powered agricultural data collection devices to provide agricultural resources where needed within localized agricultural areas within a larger agricultural area. At times, the agricultural management method may include an adaptive method that employs machine learning principles to optimize agricultural production within the agricultural area.Type: ApplicationFiled: December 24, 2015Publication date: June 29, 2017Applicant: Intel CorporationInventor: Sandeep K. Jain
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Patent number: 8289797Abstract: A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus reducing the amount of power consumed during refresh.Type: GrantFiled: October 31, 2007Date of Patent: October 16, 2012Assignee: Intel CorporationInventors: Sandeep K Jain, Animesh Mishra, John B Halbert
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Patent number: 7958380Abstract: In one embodiment, the present invention includes a method determining if an access queue associated with a channel of a memory has been empty for a predetermined time period and if so, de-asserting a clock enable signal for all ranks of the channel of the memory, otherwise providing a next memory access request from the access queue to the channel of the memory. Other embodiments are described and claimed.Type: GrantFiled: May 22, 2007Date of Patent: June 7, 2011Assignee: Intel CorporationInventors: Sandeep K. Jain, Howard David, Udayan Mukherjee
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Publication number: 20080294928Abstract: In one embodiment, the present invention includes a method determining if an access queue associated with a channel of a memory has been empty for a predetermined time period and if so, de-asserting a clock enable signal for all ranks of the channel of the memory, otherwise providing a next memory access request from the access queue to the channel of the memory. Other embodiments are described and claimed.Type: ApplicationFiled: May 22, 2007Publication date: November 27, 2008Inventors: Sandeep K. Jain, Howard David, Udayan Mukherjee
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Patent number: 7436727Abstract: In one embodiment, a method is provided. The method comprises upon entering a self-refresh mode, refreshing memory cells in a memory device at a first refresh frequency; and upon a predefined event refreshing the memory cells at a second refresh frequency, while in the self-refresh mode.Type: GrantFiled: September 30, 2004Date of Patent: October 14, 2008Assignee: Intel CorporationInventors: Sandeep K. Jain, Animesh Mishra, Jun Shi
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Patent number: 7342841Abstract: A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus reducing the amount of power consumed during refresh.Type: GrantFiled: December 21, 2004Date of Patent: March 11, 2008Assignee: Intel CorporationInventors: Sandeep K. Jain, Animesh Mishra, John B. Halbert
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Patent number: 7145823Abstract: In one embodiment, a method includes periodically charging a capacitor mounted on an electronic component; initializing a timer to count down from a counter value, once the capacitor is charged; determining if the capacitor has discharged before the timer has counted down to zero; and if the capacitor has discharged before the timer has counted down to zero then generating an interrupt.Type: GrantFiled: June 30, 2004Date of Patent: December 5, 2006Assignee: Intel CorporationInventors: Sandeep K. Jain, Animesh Mishra
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Patent number: 7099735Abstract: In one embodiment a memory controller is provided. The memory controller comprises a predictive logic circuit to predict an increase in a current operating temperature of a memory device coupled to the memory controller, based on memory cycles to be issued to the memory device; and a temperature control circuit to perform a temperature control operation wherein if the sum of the current operating temperature and the predicted increase in temperature is greater than a threshold temperature associated with the memory device, then the number of memory cycles issued to the memory device is reduced.Type: GrantFiled: June 30, 2004Date of Patent: August 29, 2006Assignee: Intel CorporationInventors: Sandeep K. Jain, George Vergis, Animesh Mishra, Jun Shi
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Patent number: 6275088Abstract: A method and apparatus is disclosed for reducing ringing of a digital signal delivered over a transmission line. A clamping circuit implemented in accordance with one embodiment of the invention includes a delay circuit. The delay circuit receives an input signal delivered over a transmission line and delivers a second signal after a preselected delay. A driver circuit receives the second signal and the input signal and provides an enable signal to a transistor for a period of time corresponding to the preselected delay. The transistor is coupled between a supply voltage and the transmission line. An inverter having an input and an output is also included, with the input of the inverter electrically connected to the transmission line. An additional transistor is electrically coupled between the supply voltage and the transmission line.Type: GrantFiled: December 29, 1997Date of Patent: August 14, 2001Assignee: Intel CorporationInventor: Sandeep K. Jain
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Patent number: 5999020Abstract: A high-speed, differential pair input buffer is constructed from a conventional differential pair having a data input terminal, a reference voltage input terminal, and an output terminal. A voltage source Vsupply and its ground connection are coupled to the differential pair through a first pair of transistors. The first pair of transistors have their enable inputs coupled to the data input terminal so that they are both biased "on" during a transition in a logic signal delivered to the data input terminal. The output terminal of the differential pair is connected through a delay circuit to the enable input terminals of a second pair of transistors, which also interconnect the differential pair to the voltage source V.sub.supply and system ground. Thus, the second pair of transistors provide a feedback path to enable the differential pair to conduct current longer if a load connected to the output of the differential pair slows the transition of the output of the differential pair.Type: GrantFiled: November 25, 1997Date of Patent: December 7, 1999Assignee: Intel CorporationInventors: Andrew M. Volk, Sandeep K. Jain
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Patent number: 5994919Abstract: A clamping circuit is provided to reduce ringing of digital signals delivered over a transmission line. The clamping circuit includes a pair of transistors respectively connecting the transmission line to a pair of voltage supplies, such as a V.sub.supply and ground. The transistors are controllably enabled to connect the transmission line to V.sub.supply or ground in response to a transition in the digital signal present on the transmission line. That is, the transistor interconnecting the transmission line to ground is controllably enabled in response to a high-to-low transition so as to counteract ringing on the transmission line. Alternately, the transistor interconnecting the transmission line to V.sub.supply is controllably enabled in response to a low-to-high transition so as to counteract ringing on the transmission line.Type: GrantFiled: September 30, 1997Date of Patent: November 30, 1999Assignee: Intel CorporationInventor: Sandeep K. Jain