Patents by Inventor Sandeep Kakarlapudi
Sandeep Kakarlapudi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240169644Abstract: When performing tile-based rendering a first, pre-pass operation in which primitives in a sequence of primitives for a tile are processed to determine visibility information for the sequence of primitives, the visibility information being usable to determine whether or not fragments for a primitive in the sequence of primitives should subsequently be processed further for the render output, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted. The visibility information comprises the depth buffer.Type: ApplicationFiled: November 15, 2023Publication date: May 23, 2024Applicant: Arm LimitedInventors: Tord Kvestad Øygard, Sandeep Kakarlapudi, Toni Viki Brkic, William Robert Stoye
-
Publication number: 20240169646Abstract: When performing tile-based rendering a first, pre-pass operation in which primitives in a sequence of primitives for a tile are processed to determine visibility information for the sequence of primitives, the visibility information being usable to determine whether or not fragments for a primitive in the sequence of primitives should subsequently be processed further for the render output, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted. The first, pre-pass can be stopped to process primitives in a fail-safe manner if necessary.Type: ApplicationFiled: November 15, 2023Publication date: May 23, 2024Applicant: Arm LimitedInventors: Tord Kvestad Øygard, Sandeep Kakarlapudi
-
Publication number: 20240169663Abstract: When performing tile-based rendering a first, pre-pass operation in which primitives in a sequence of primitives for a tile are processed to determine visibility information for the sequence of primitives, the visibility information being usable to determine whether or not fragments for a primitive in the sequence of primitives should subsequently be processed further for the render output, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted. The visibility information indicates which primitives should be rendered for which sampling positions of the render output.Type: ApplicationFiled: November 17, 2022Publication date: May 23, 2024Applicant: Arm LimitedInventors: Tord Kvestad Øygard, Philip Carlos Garcia, Sandeep Kakarlapudi
-
Publication number: 20240169648Abstract: When performing tile-based rendering a first, pre-pass operation in which primitives for a tile are processed to determine visibility information, the visibility information being usable to determine whether fragments for a primitive in the sequence of primitives should subsequently be processed further for the render output, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted. The visibility information indicates which primitives should be rendered for which sampling positions of the render output in a hierarchical manner.Type: ApplicationFiled: November 15, 2023Publication date: May 23, 2024Applicant: Arm LimitedInventors: Ole Magnus Ruud, Sandeep Kakarlapudi, Tord Kvestad Øygard, Per Kristian Kjøll
-
Publication number: 20240169618Abstract: When performing tile-based rendering a first, pre-pass operation in which primitives for a tile are processed to determine visibility information, the visibility information usable to determine whether or not fragments for a primitive should subsequently be processed further for the render output, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted. The visibility information indicates which primitives should be rendered for which sampling positions of the render output in a hierarchical manner.Type: ApplicationFiled: November 15, 2023Publication date: May 23, 2024Applicant: Arm LimitedInventors: Ole Magnus Ruud, Sandeep Kakarlapudi, Tord Kvestad Øygard, Per Kristian Kjøll
-
Publication number: 20240169619Abstract: When performing tile-based rendering a first, pre-pass operation in which primitives in a sequence of primitives for a tile are processed to determine visibility information for the sequence, the visibility information being usable to determine whether fragments for a primitive in the sequence should subsequently be processed further, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted. The visibility information indicates which primitives should be rendered for which sampling positions of the render output in a hierarchical manner.Type: ApplicationFiled: November 15, 2023Publication date: May 23, 2024Applicant: Arm LimitedInventors: Ole Magnus Ruud, Sandeep Kakarlapudi, Tord Kvestad Øygard, Per Kristian Kjøll, Toni Viki Brkic
-
Patent number: 11972503Abstract: A method of operating a graphics processor that executes a graphics processing pipeline that includes an early culling tester that can access plural different culling test data buffers is disclosed. Information is maintained indicating which of the plural culling test data buffers is expected to be accessed, and the information is used to control the early culling tester. The information may be used to control the early culling tester such that processing delays associated with waiting for dependencies to resolve are reduced.Type: GrantFiled: May 6, 2022Date of Patent: April 30, 2024Assignee: Arm LimitedInventors: Toni Viki Brkic, Sandeep Kakarlapudi, Tord Kvestad Øygard, Saurav Arjun
-
Publication number: 20230401667Abstract: A method of operating a graphics processor to process sets of geometry to generate an output. Each set of geometry is associated with lower level geometry including vertex data to be used when rendering the geometry as well a separate higher level representation of the geometry. The higher level representations of the geometry can be obtained by the graphics processor independently of the other, lower level geometry and used to determine which sets of geometry should be processed for which regions of the output. Once this determination is made, the regions can be rendered by obtaining and processing the lower level geometry accordingly.Type: ApplicationFiled: October 19, 2021Publication date: December 14, 2023Inventors: Sandeep KAKARLAPUDI, Andreas ENGH-HALSTVEDT, Frank Klaeboe LANGTIND
-
Publication number: 20220358616Abstract: A method of operating a graphics processor that executes a graphics processing pipeline that includes an early culling tester that can access plural different culling test data buffers is disclosed. Information is maintained indicating which of the plural culling test data buffers is expected to be accessed, and the information is used to control the early culling tester. The information may be used to control the early culling tester such that processing delays associated with waiting for dependencies to resolve are reduced.Type: ApplicationFiled: May 6, 2022Publication date: November 10, 2022Inventors: Toni Viki BRKIC, Sandeep KAKARLAPUDI, Tord Kvestad ØYGARD, Saurav ARJUN
-
Patent number: 11250620Abstract: A method of operating a graphics processor that comprises a renderer that can render primitives to generate a render output using different shading rates is disclosed. A shading rate for rendering a primitive is determined based on a depth value for the primitive. This can reduce processing effort required to render a render output while maintaining an acceptable image quality.Type: GrantFiled: June 9, 2020Date of Patent: February 15, 2022Assignee: Arm LimitedInventors: Olof Henrik Uhrenholt, Sandeep Kakarlapudi
-
Publication number: 20210383600Abstract: A method of operating a graphics processor that comprises a renderer that can render primitives to generate a render output using different shading rates is disclosed. A shading rate for rendering a primitive is determined based on a depth value for the primitive. This can reduce processing effort required to render a render output while maintaining an acceptable image quality.Type: ApplicationFiled: June 9, 2020Publication date: December 9, 2021Applicant: Arm LimitedInventors: Olof Henrik Uhrenholt, Sandeep Kakarlapudi
-
Patent number: 11010959Abstract: When performing foveated rendering, a graphics processor is controlled to render plural, e.g. three, different resolution versions from the same viewpoint for a scene. The rendered different resolution images are then appropriately combined (composited) to provide the output “foveated” image (output frame) that is displayed. The geometry for the scene is processed and sorted into lists for respective rendering tiles of the images being rendered only once, to provide a single set of tile geometry lists that are then used in common when rendering each respective resolution image.Type: GrantFiled: April 25, 2017Date of Patent: May 18, 2021Assignee: Arm LimitedInventors: Sandeep Kakarlapudi, Andreas Engh-Halstvedt, Samuel Martin, Edvard Fielding
-
Patent number: 10861125Abstract: When a processing resource of a data processing system is to perform processing tasks for applications executing on a host processor, the host processor prepares a plurality of command streams to cause the processing resource to perform the processing tasks. When a processing task to be added to a command stream has a dependency on a processing task or tasks that will be included in another command stream, a wait command is added to the command stream that is to include the processing task that has a dependency on a processing task or tasks that will be included in the another command stream, to cause the processing resource to delay executing subsequent commands in the command stream after the wait command, until the processing resource has reached a particular position in the another command stream.Type: GrantFiled: May 2, 2019Date of Patent: December 8, 2020Assignee: Arm LimitedInventors: Arne Aas, Sandeep Kakarlapudi, Hakan Lars-Goran Persson
-
Patent number: 10824468Abstract: A method of controlling a data processor to perform data processing operations is disclosed in which a host processor prepares one or more queue(s) of operations for execution by the data processor. When an error is encountered in the processing of an operation for one of the one or more queue(s), a queue can be set into an error state in which instructions that may have a data dependency on another operation are not executed. The host processor includes in the queues error barrier instructions that divide the respective queues into sets of operations between which there are no data processing dependencies. An error state for a queue can thus be cleared when its processing reaches the next error barrier instruction in the queue.Type: GrantFiled: February 12, 2019Date of Patent: November 3, 2020Assignee: Arm LimitedInventors: Mark Underwood, Sandeep Kakarlapudi, Robert John Rees
-
Patent number: 10803547Abstract: In a graphics processing system, an application executing on a host processor can request graphics processing operations that are to be performed by only subsets of the set of stages of a graphics processing pipeline implemented by a graphics processor. In response to such a request, the driver for the graphics processor causes the graphics processing operation that is to be performed using only a subset of the set of stages of the graphics processing pipeline to be performed. The driver can cause the graphics processing operation that is to be performed by the subset of stages of the graphics processing pipeline to be performed by the graphics processor, or on the host processor.Type: GrantFiled: November 6, 2017Date of Patent: October 13, 2020Assignee: Arm LimitedInventor: Sandeep Kakarlapudi
-
Publication number: 20200257555Abstract: A method of controlling a data processor to perform data processing operations is disclosed in which a host processor prepares one or more queue(s) of operations for execution by the data processor. When an error is encountered in the processing of an operation for one of the one or more queue(s), a queue can be set into an error state in which instructions that may have a data dependency on another operation are not executed. The host processor includes in the queues error barrier instructions that divide the respective queues into sets of operations between which there are no data processing dependencies. An error state for a queue can thus be cleared when its processing reaches the next error barrier instruction in the queue.Type: ApplicationFiled: February 12, 2019Publication date: August 13, 2020Applicant: Arm LimitedInventors: Mark Underwood, Sandeep Kakarlapudi, Robert John Rees
-
Patent number: 10607400Abstract: A graphics processing pipeline comprises vertex shading circuitry that operates to vertex shade position attributes of vertices of a set of vertices to be processed by the graphics processing pipeline, to generate, inter alia, a separate vertex shaded position attribute value for each view of the plural different views. Tiling circuitry then determines for the vertices that have been subjected to the first vertex shading operation, whether the vertices should be processed further. Vertex shading circuitry then performs a second vertex shading operation on the vertices that it has been determined should be processed further, to vertex shade the remaining vertex attributes for each vertex that it has been determined should be processed further, to generate, inter alia, a single vertex shaded attribute value for the set of plural views.Type: GrantFiled: May 15, 2017Date of Patent: March 31, 2020Assignee: Arm LimitedInventors: Sandeep Kakarlapudi, Jorn Nystad, Andreas Due-Engh Halstvedt
-
Publication number: 20190340722Abstract: When a processing resource of a data processing system is to perform processing tasks for applications executing on a host processor, the host processor prepares a plurality of command streams to cause the processing resource to perform the processing tasks. When a processing task to be added to a command stream has a dependency on a processing task or tasks that will be included in another command stream, a wait command is added to the command stream that is to include the processing task that has a dependency on a processing task or tasks that will be included in the another command stream, to cause the processing resource to delay executing subsequent commands in the command stream after the wait command, until the processing resource has reached a particular position in the another command stream.Type: ApplicationFiled: May 2, 2019Publication date: November 7, 2019Applicant: Arm LimitedInventors: Arne Aas, Sandeep Kakarlapudi, Hakan Lars-Goran Persson
-
Patent number: 10432914Abstract: A graphics processing system includes a graphics processing pipeline, which includes a primitive generation stage and a pixel processing stage. The graphics processing system is arranged to process input data in the primitive generation stage to produce first primitive data associated with a first view of a scene and second primitive data associated with a second view of the scene. The graphics processing system is arranged to process the first primitive data in the pixel processing stage to produce first pixel-processed data associated with the first view. The graphics processing system is arranged to determine, for second pixel-processed data associated with the second view, whether to use the first pixel-processed data as the second pixel-processed data or whether to process the second primitive data in the pixel processing stage to produce the second pixel-processed data, and perform additional processing in the graphics processing pipeline based on the determining.Type: GrantFiled: August 22, 2017Date of Patent: October 1, 2019Assignee: Arm LimitedInventors: Peter William Harris, Robin Paul Fell, Sandeep Kakarlapudi
-
Patent number: 10255718Abstract: A graphics processing pipeline includes position shading circuitry, a tiler, varying-only vertex shading circuitry and fragment (frontend) shading circuitry. The tiler reads a list of indices defining a set of vertices to be processed by the graphics processing pipeline and determines whether or not vertex shading is required for the positional attributes of the vertices. If vertex shading is required, the tiler sends a position shading request for the vertices to the position shading circuitry. The tiler uses the vertex shaded position data to identify primitives that should be processed further to generate the render output and that accordingly should be subjected to a second, varying shading, vertex shading operation. When the tiler determines that a vertex (or group of vertices) should be subjected to the second, varying shading, vertex shading operation, the tiler sends a varying shading request for the vertex (or vertices) to the varying shading circuitry.Type: GrantFiled: December 28, 2016Date of Patent: April 9, 2019Assignee: Arm LimitedInventors: Frank Langtind, Andreas Due Engh-Halstvedt, Sandeep Kakarlapudi