Patents by Inventor Sang-bum Kang

Sang-bum Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070269974
    Abstract: A metal contact in a semiconductor device is formed by forming an insulating layer having a contact hole therein on a silicon layer. A cobalt layer is formed on a bottom and inner walls of the contact hole. A cobalt silicide layer is formed at the bottom of the contact hole while forming a titanium layer on the cobalt layer. A plug is formed on the titanium layer so as to fill the contact hole.
    Type: Application
    Filed: May 29, 2007
    Publication date: November 22, 2007
    Inventors: Hee-sook Park, Gil-heyun Choi, Sang-bum Kang, Seong-geon Park, Kwang-jin Moon
  • Publication number: 20070197015
    Abstract: A metal contact in a semiconductor device is formed by forming an insulating layer having a contact hole therein on a silicon substrate. A cobalt layer is formed on a bottom and inner walls of the contact hole. A cobalt silicide layer is formed at the bottom of the contact hole while forming a titanium layer on the cobalt layer. A plug is formed on the titanium layer so as to fill the contact hole.
    Type: Application
    Filed: April 17, 2007
    Publication date: August 23, 2007
    Inventors: Hee-sook Park, Gil-heyun Choi, Sang-bum Kang, Seong-geon Park, Kwang-jin Moon
  • Patent number: 7223689
    Abstract: A metal contact in a semiconductor device is formed by forming an insulating layer having a contact hole therein on a silicon substrate. A cobalt layer is formed on a bottom and inner walls of the contact hole. A cobalt silicide layer is formed at the bottom of the contact hole while forming a titanium layer on the cobalt layer. A plug is formed on the titanium layer so as to fill the contact hole.
    Type: Grant
    Filed: April 22, 2005
    Date of Patent: May 29, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-sook Park, Gil-heyun Choi, Sang-bum Kang, Seong-geon Park, Kwang-jin Moon
  • Patent number: 7067420
    Abstract: A metal layer is formed on an integrated circuit device including forming an insulating layer on an integrated circuit substrate. A contact hole is formed by selectively etching the insulating layer to thereby partially expose the substrate. A metal layer including tantalum nitride is formed on the insulating layer including the contact hole using a tantalum precursor including a tantalum element and at least one bonding element that is chemically bonded to the tantalum element. A part of the at least one bonding element include at least one ligand bonding element that is ligand-bonded to the tantalum element. Forming the metal layer may include removing at least some of the ligand bonded elements with a removing gas that is substantially free of hydrogen radicals. The metal layer may be formed using a chemical vapor deposition (CVD) or an atomic layer deposition (ALD) process. A copper or other metal layer may be deposited on the metal layer including tantalum nitride.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: June 27, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-In Choi, Gil-Heyun Choi, Byung-Hee Kim, Sang-Bum Kang
  • Patent number: 7051934
    Abstract: Methods of forming a metal layer in integrated circuit devices using selective electroplating in a recess are disclosed. In particular, a recess is formed in a surface of an insulating layer. The recess has a side wall inside the recess, a bottom inside the recess, and an edge at a boundary of the surface of the insulating layer and the side wall. A selective electroplating mask is formed on the side wall to provide a covered portion of the side wall and an exposed portion of the side wall. The exposed portion of the side wall can be electroplated with a metal. Related conductive contacts are also disclosed.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: May 30, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo-jong Lee, Seung-man Choi, Sang-bum Kang, Gil-heyun Choi
  • Publication number: 20050186784
    Abstract: A metal contact in a semiconductor device is formed by forming an insulating layer having a contact hole therein on a silicon substrate. A cobalt layer is formed on a bottom and inner walls of the contact hole. A cobalt silicide layer is formed at the bottom of the contact hole while forming a titanium layer on the cobalt layer. A plug is formed on the titanium layer so as to fill the contact hole.
    Type: Application
    Filed: April 22, 2005
    Publication date: August 25, 2005
    Inventors: Hee-sook Park, Gil-heyun Choi, Sang-bum Kang, Seong-geon Park, Kwang-jin Moon
  • Publication number: 20050009333
    Abstract: Methods of forming a metal layer in integrated circuit devices using selective electroplating in a recess are disclosed. In particular, a recess is formed in a surface of an insulating layer. The recess has a side wall inside the recess, a bottom inside the recess, and an edge at a boundary of the surface of the insulating layer and the side wall. A selective electroplating mask is formed on the side wall to provide a covered portion of the side wall and an exposed portion of the side wall. The exposed portion of the side wall can be electroplated with a metal. Related conductive contacts are also disclosed.
    Type: Application
    Filed: August 10, 2004
    Publication date: January 13, 2005
    Inventors: Hyo-jong Lee, Seung-man Choi, Sang-bum Kang, Gil-heyun Choi
  • Patent number: 6821572
    Abstract: After a processing chamber is used to deposit a refractory metal film on a substrate, the chamber is plasma-treated with a gas including either nitrogen and/or hydrogen and in-situ cleaned. By plasma-treating the chamber with a gas including nitrogen, the refractory metal film that forms on interior surfaces of the chamber during substrate processing is nitrided. The nitrided refractory metal film can be removed from the chamber during the in-situ cleaning. By plasma-treating the chamber with a gas including hydrogen, reaction by-products generated in the chamber is diluted removed. The chamber may be plasma-treated in a gas ambient including both nitrogen and hydrogen. Also, the plasma treatment may be performed before and after the in-situ cleaning.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: November 23, 2004
    Assignee: Samsung Electronics Co., LTD
    Inventors: Kwang-Jin Moon, Gil-Heyun Choi, Sang-Bum Kang, Hee-Sook Park
  • Publication number: 20040224506
    Abstract: Methods of forming metal layers include techniques to form metal layers using atomic layer deposition techniques that may be repeated in sequence to build up multiple atomic metal layers into a metal thin film. The methods include forming a metal layer by chemisorbing a metallic precursor comprising a metal element and at least one non-metal element that is ligand-bonded to the metal element, on a substrate. The metal element may include tantalum. The chemisorbed metallic precursor is then converted into the metal layer by removing the at least one non-metal element from the metallic precursor through ligand exchange. This removal of the non-metal element may be achieved by exposing the chemisorbed metallic precursor to an activated gas that is established by a remote plasma, which reduces substrate damage. The activated gas may be selected from the group consisting of H2, NH3, SiH4 and Si2H6 and combinations thereof. These steps may be performed at a temperature less than about 650° C.
    Type: Application
    Filed: June 8, 2004
    Publication date: November 11, 2004
    Inventors: Kyung-In Choi, Sang-Bum Kang, Byung-Hee Kim, Gil-Heyun Choi
  • Patent number: 6806135
    Abstract: The present invention discloses a method of manufacturing a semiconductor device having an upper capacitor electrode and a node resistor, including depositing a thin film at a first deposition rate on an edge portion of a wafer and at a second deposition rate on a central portion of the wafer to form the upper capacitor electrode and the node resistor, thereby improving step coverage of the upper capacitor electrode while simultaneously improving resistance distribution of the node resistor.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: October 19, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Seok Lim, In-Sun Park, Sang-Bum Kang, Jong-sik Chun, Seong-Geon Park, In-Su Ha
  • Patent number: 6787460
    Abstract: Methods of forming a metal layer in integrated circuit devices using selective electroplating in a recess are disclosed. In particular, a recess is formed in a surface of an insulating layer. The recess has a side wall inside the recess, a bottom inside the recess, and an edge at a boundary of the surface of the insulating layer and the side wall. A selective electroplating mask is formed on the side wall to provide a covered portion of the side wall and an exposed portion of the side wall. The exposed portion of the side wall can be electroplated with a metal. Related conductive contacts are also disclosed.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: September 7, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo-jong Lee, Seung-man Choi, Sang-bum Kang, Gil-heyun Choi
  • Publication number: 20040043601
    Abstract: A metal contact in a semiconductor device is formed by forming an insulating layer having a contact hole therein on a silicon substrate. A cobalt layer is formed on a bottom and inner walls of the contact hole. A cobalt silicide layer is formed at the bottom of the contact hole while forming a titanium layer on the cobalt layer. A plug is formed on the titanium layer so as to fill the contact hole.
    Type: Application
    Filed: July 8, 2003
    Publication date: March 4, 2004
    Inventors: Hee-Sook Park, Gil-Heyun Choi, Sang-Bum Kang, Seong-Geon Park, Kwang-Jin Moon
  • Publication number: 20040038517
    Abstract: A contact structure is formed by forming an interlayer dielectric on a substrate having a semiconductive region. A contact hole is formed in the interlayer dielectric to expose the semiconductive region. A conductive structure is formed adjacent to the contact hole. Spacers are formed on inner sidewalls of the contact hole. A cobalt silicide layer is formed at a bottom of the contact hole. The spacers are configured to electrically isolate the cobalt silicide layer from the conductive structure. A conductive layer is formed on the cobalt silicide layer in the contact hole.
    Type: Application
    Filed: June 30, 2003
    Publication date: February 26, 2004
    Inventors: Sang-Bum Kang, Kwang-Jin Moon, Seung-Gil Yang, Hee-Sook Park
  • Publication number: 20040013818
    Abstract: After a processing chamber is used to deposit a refractory metal film on a substrate, the chamber is plasma-treated with a gas including either nitrogen and/or hydrogen and in-situ cleaned. By plasma-treating the chamber with a gas including nitrogen, the refractory metal film that forms on interior surfaces of the chamber during substrate processing is nitrided. The nitrided refractory metal film can be removed from the chamber during the in-situ cleaning. By plasma-treating the chamber with a gas including hydrogen, reaction by-products generated in the chamber is diluted and removed. The chamber may be plasma-treated in a gas ambient including both nitrogen and hydrogen. Also, the plasma treatment may be performed before and after the in-situ cleaning.
    Type: Application
    Filed: March 4, 2003
    Publication date: January 22, 2004
    Inventors: Kwang-Jin Moon, Gil-Heyun Choi, Sang-Bum Kang, Hee-Sook Park
  • Publication number: 20030219942
    Abstract: Methods of forming a capacitor can include forming a capacitor electrode including tantalum nitride. The capacitor electrode can be formed using a tantalum precursor including tantalum elements and bonding elements that are chemically bonded to the tantalum elements. Moreover, the tantalum precursor can include at least one of a tantalum amine derivative and/or a tantalum halide derivative. Related methods of forming integrated circuit devices are also discussed.
    Type: Application
    Filed: April 7, 2003
    Publication date: November 27, 2003
    Inventors: Kyung-In Choi, Gil-Heyun Choi, Byung-Hee Kim, Sang-Bum Kang
  • Publication number: 20030219979
    Abstract: A metal layer is formed on an integrated circuit device including forming an insulating layer on an integrated circuit substrate. A contact hole is formed by selectively etching the insulating layer to thereby partially expose the substrate. A metal layer including tantalum nitride is formed on the insulating layer including the contact hole using a tantalum precursor including a tantalum element and at least one bonding element that is chemically bonded to the tantalum element. A part of the at least one bonding element include at least one ligand bonding element that is ligand-bonded to the tantalum element. Forming the metal layer may include removing at least some of the ligand bonded elements with a removing gas that is substantially free of hydrogen radicals. The metal layer may be formed using a chemical vapor deposition (CVD) or an atomic layer deposition (ALD) process. A copper or other metal layer may be deposited on the metal layer including tantalum nitride.
    Type: Application
    Filed: April 1, 2003
    Publication date: November 27, 2003
    Inventors: Kyung-In Choi, Gil-Heyun Choi, Byung-Hee Kim, Sang-Bum Kang
  • Publication number: 20030134510
    Abstract: Methods of forming a metal layer in integrated circuit devices using selective electroplating in a recess are disclosed. In particular, a recess is formed in a surface of an insulating layer. The recess has a side wall inside the recess, a bottom inside the recess, and an edge at a boundary of the surface of the insulating layer and the side wall. A selective electroplating mask is formed on the side wall to provide a covered portion of the side wall and an exposed portion of the side wall. The exposed portion of the side wall can be electroplated with a metal. Related conductive contacts are also disclosed.
    Type: Application
    Filed: January 14, 2002
    Publication date: July 17, 2003
    Inventors: Hyo-Jong Lee, Seung-Man Choi, Sang-Bum Kang, Gil-Heyun Choi
  • Publication number: 20030124798
    Abstract: The present invention discloses a method of manufacturing a semiconductor device having an upper capacitor electrode and a node resistor, including depositing a thin film at a first deposition rate on an edge portion of a wafer and at a second deposition rate on a central portion of the wafer to form the upper capacitor electrode and the node resistor, thereby improving step coverage of the upper capacitor electrode while simultaneously improving resistance distribution of the node resistor.
    Type: Application
    Filed: December 26, 2002
    Publication date: July 3, 2003
    Inventors: Hyun-Seok Lim, In-Sun Park, Sang-Bum Kang, Jong-sik Chun, Seong-Geon Park, In-Su Ha
  • Publication number: 20030017697
    Abstract: Methods of forming metal layers include techniques to form metal layers using atomic layer deposition techniques that may be repeated in sequence to build up multiple atomic metal layers into a metal thin film. The methods include forming a metal layer by chemisorbing a metallic precursor comprising a metal element and at least one non-metal element that is ligand-bonded to the metal element, on a substrate. The metal element may include tantalum. The chemisorbed metallic precursor is then converted into the metal layer by removing the at least one non-metal element from the metallic precursor through ligand exchange. This removal of the non-metal element may be achieved by exposing the chemisorbed metallic precursor to an activated gas that is established by a remote plasma, which reduces substrate damage. The activated gas may be selected from the group consisting of H2, NH3, SiH4 and Si2H6 and combinations thereof. These steps may be performed at a temperature less than about 650° C.
    Type: Application
    Filed: July 17, 2002
    Publication date: January 23, 2003
    Inventors: Kyung-In Choi, Sang-Bum Kang, Byung-Hee Kim, Gil-Heyun Choi
  • Patent number: 6372598
    Abstract: A selective metal layer formation method, a capacitor formation method using the same, and a method of forming an ohmic layer on a contact hole and filling the contact hole using the same, are provided. A sacrificial metal layer is selectively deposited on a conductive layer by supplying a sacrificial metal source gas which deposits selectively on a semiconductor substrate having an insulating film and the conductive layer. Sacrificial metal atoms and a halide are formed, and the sacrificial metal layer is replaced with a deposition metal layer such as titanium Ti or platinum Pt, by supplying a metal halide gas having a halogen coherence smaller than the halogen coherence of the metal atoms in the sacrificial metal layer. If such a process is used to form a capacitor lower electrode or form an ohmic layer on the bottom of a contact hole, a metal layer can be selectively formed at a temperature of 500° C. or lower.
    Type: Grant
    Filed: June 16, 1999
    Date of Patent: April 16, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-bum Kang, Yun-sook Chae, Sang-in Lee, Hyun-seok Lim, Mee-young Yoon