Abstract: A circuit for testing a high speed data bus comprises a test port, a data bus port, a signal generator, a polarity monitor, and an attenuation monitor. The test port is coupled to a test controller. The data bus port is coupled to the data bus. The signal generator may generate a test signal to the data bus port at a first voltage level with a duty cycle of fifty percent or greater. The polarity monitor may receive the test signal from the data bus port and generate a voltage that is proportional to the duty cycle and indicative of a polarity of a portion of the data bus. The attenuation monitor may receive the test signal from either the signal generator or the data bus port and determine a second voltage level of the received test signal, with the second voltage level being communicated to the test port.

Abstract: A circuit for testing a high speed data bus comprises a test port, a data bus port, a signal generator, a polarity monitor, and an attenuation monitor. The test port is coupled to a test controller. The data bus port is coupled to the data bus. The signal generator may generate a test signal to the data bus port at a first voltage level with a duty cycle of fifty percent or greater. The polarity monitor may receive the test signal from the data bus port and measure a voltage proportional to the duty cycle to determine a polarity of a portion of the data bus, with the voltage level representative of the polarity being communicated to the test port. The attenuation monitor may receive the test signal from either the signal generator or the data bus port and determine a second voltage level of the received test signal, with the second voltage level being communicated to the test port.