Patents by Inventor Sang-chul Kang
Sang-chul Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8811087Abstract: A nonvolatile memory device comprises a memory cell array and a voltage generator. The memory cell array comprises a plurality of memory cells connected in series between a string selection transistor connected to a bit line and a ground selection transistor connected to a source line. The voltage generator provides read voltages to word lines of memory cells selected from among the plurality of memory cells during a read operation. The read voltages of the selected memory cells differ from each other according to their respective distances from the string selection transistor.Type: GrantFiled: November 8, 2011Date of Patent: August 19, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-jin Yun, Sang-chul Kang
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Patent number: 8755224Abstract: A nonvolatile memory device comprises a memory cell array, a page buffer, and a bit line connection signal controller. The memory cell array comprises a plurality of word lines and bit lines arranged in rows and columns, and a plurality of memory cells connected to the respective word lines and bit lines. The page buffer connects a selected bit line among the plurality of bit lines to the page buffer, applies a precharge voltage to the selected bit line, and senses a voltage of the selected bit line after developing of the selected bit line according to a bit line connection signal, during a read operation. The bit line connection signal controller changes the bit line connection signal according to a control signal, during the read operation.Type: GrantFiled: January 26, 2012Date of Patent: June 17, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-jin Yun, Sang-chul Kang, Seung-jae Lee
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Patent number: 8621266Abstract: A memory system comprises a flash memory and a memory controller. The flash memory comprises a plurality of memory blocks. The memory controller performs a read retry operation on a memory block containing an uncorrectable read error until an accurate data value is read from the memory block. The memory controller then controls the flash memory to perform an erase refresh operation on the memory block.Type: GrantFiled: July 23, 2010Date of Patent: December 31, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Sang chul Kang, Seung hyun Han
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Publication number: 20120213003Abstract: A nonvolatile memory device comprises a memory cell array, a page buffer, and a bit line connection signal controller. The memory cell array comprises a plurality of word lines and bit lines arranged in rows and columns, and a plurality of memory cells connected to the respective word lines and bit lines. The page buffer connects a selected bit line among the plurality of bit lines to the page buffer, applies a precharge voltage to the selected bit line, and senses a voltage of the selected bit line after developing of the selected bit line according to a bit line connection signal, during a read operation. The bit line connection signal controller changes the bit line connection signal according to a control signal, during the read operation.Type: ApplicationFiled: January 26, 2012Publication date: August 23, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-jin YUN, Sang-chul KANG, Seung-jae LEE
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Publication number: 20120213004Abstract: A nonvolatile memory device comprises a memory cell array and a voltage generator. The memory cell array comprises a plurality of memory cells connected in series between a string selection transistor connected to a bit line and a ground selection transistor connected to a source line. The voltage generator provides read voltages to word lines of memory cells selected from among the plurality of memory cells during a read operation. The read voltages of the selected memory cells differ from each other according to their respective distances from the string selection transistor.Type: ApplicationFiled: November 8, 2011Publication date: August 23, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-jin Yun, Sang-chul Kang
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Patent number: 8205167Abstract: A method and system for providing an advertisement window in a certain area of a web browser executed in a user terminal, wherein the user terminal being communicated with at least one advertiser server and an advertisement control server over the Internet. The method includes the steps of requesting a user identification code; receiving the user identification code from the advertisement control server, and storing the code on the local storage of the user terminal; requesting advertisement control data to the advertisement control server using the stored user identification; receiving the advertisement control data from the advertisement control server, and displaying control information of the advertisement window; accessing and obtaining the advertisement data located on the received address; and placing, in a certain area of the web browser.Type: GrantFiled: October 2, 2002Date of Patent: June 19, 2012Assignee: International Business Machines CorporationInventors: Sang Chul Kang, Chang Woo Min
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Patent number: 7949819Abstract: According to an example embodiment, a method of changing a block size in a flash memory device having a multi-plane scheme may include decoding an external input address and changing the block size of the flash memory device from a first block size to a second block size. The external input address may be decoded into a block address and a page address. The block size of the flash memory device may be changed from the first block size to the second block size by shifting at least one bit of the block address to the page address or shifting at least one bit of the page address to the block address.Type: GrantFiled: October 30, 2007Date of Patent: May 24, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-chul Kang, Jin-yub Lee
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Publication number: 20110066899Abstract: A memory system comprises a flash memory and a memory controller. The flash memory comprises a plurality of memory blocks. The memory controller performs a read retry operation on a memory block containing an uncorrectable read error until an accurate data value is read from the memory block. The memory controller then controls the flash memory to perform an erase refresh operation on the memory block.Type: ApplicationFiled: July 23, 2010Publication date: March 17, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang chul KANG, Seung hyun HAN
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Patent number: 7894258Abstract: A flash memory device capable of efficiently determining whether most significant bit (MSB) programming has been performed is provided. The flash memory device includes a cell array, a control unit, and a determination unit. The cell array includes at least one flag cell for storing information about whether MSB programming has been performed on a multi-level cell. The control unit controls a program operation, a read operation, and an erasure operation with respect to the cell array. The determination unit receives flag data stored in the flag cells, performs an OR operation and/or an AND operation on the flag data, and generates a determination signal based on a result of the OR operation and/or the AND operation, wherein the determination signal represents whether the MSB programming has been performed.Type: GrantFiled: August 7, 2008Date of Patent: February 22, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Taek Jeong, Sang-Chul Kang, Kyong-Ae Kim
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Patent number: 7876613Abstract: Multi-bit flash memory devices are provided. The multi-bit flash memory device includes an array of memory cells and a page buffer block including page buffers. Each of the page buffers has a single latch structure and performs a write operation with respect to memory cells according to loaded data. A buffer random access memory (RAM) is configured to store program data provided from an external host device during a multi-bit program operation. Control logic is provided that is configured to control the page buffer block and the buffer RAM so that program data stored in the buffer RAM is reloaded into the page buffer block whenever data programmed before the multi-bit program operation is compared with data to be currently programmed. The control logic is configured to store data to be programmed next in the buffer RAM before the multi-bit program operation is completed.Type: GrantFiled: July 30, 2008Date of Patent: January 25, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Chul Kang, Ho-kil Lee, Jin-Yub Lee
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Patent number: 7684241Abstract: Methods of executing a multi-page copyback program in a non-volatile memory device are provided, where the non-volatile memory device includes a memory having a plurality of memory blocks. A page of data of the memory block having a first address is replaced responsive to a generated multi-page copyback program command. It is determined if the first address of the page of data is the same as a stored address of the page at which the failure was detected. The first address is incremented if it is determined that the first address and the stored address are not the same. The pages of data are replaced, the addressed are compared and the addresses are incremented until it is determined that the incremented address and the stored address are the same. Related devices and systems are also provided herein.Type: GrantFiled: August 23, 2007Date of Patent: March 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Chul Kang, Yong-Taek Jeong
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Patent number: 7557955Abstract: A method and system are provided for producing a print that substantially corresponds to the colorimetric attributes of a corresponding proof for an electronic source file. The method and system entail creating a first raster file corresponding to the electronic source file and a second raster file corresponding to the proof. The first and second raster files are aligned to insure a spatial correlation, and a color conversion data structure is built by comparing the aligned first and second raster files. The color conversion data structure is then used to convert the first raster file to a color converted output file. The color converted output file is color transformed to an output file which is then used to produce the print. The print substantially corresponds to the colorimetric attributes of the corresponding proof for the electronic source file.Type: GrantFiled: December 27, 2005Date of Patent: July 7, 2009Assignee: Xerox CorporationInventors: Sang-Chul Kang, Robert John Rolleston, Martin Sidney Maltz, Charles Michael Hains
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Publication number: 20090147574Abstract: A flash memory device capable of efficiently determining whether most significant bit (MSB) programming has been performed is provided. The flash memory device includes a cell array, a control unit, and a determination unit. The cell array includes at least one flag cell for storing information about whether MSB programming has been performed on a multi-level cell. The control unit controls a program operation, a read operation, and an erasure operation with respect to the cell array. The determination unit receives flag data stored in the flag cells, performs an OR operation and/or an AND operation on the flag data, and generates a determination signal based on a result of the OR operation and/or the AND operation, wherein the determination signal represents whether the MSB programming has been performed.Type: ApplicationFiled: August 7, 2008Publication date: June 11, 2009Inventors: Yong Taek Jeong, Sang-Chul Kang, Kyong-Ae Kim
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Patent number: 7508730Abstract: A semiconductor device includes a memory cell array and a command interface that is configured to receive a command from outside of the semiconductor memory device. The command interface is further configured to interpret the received command and to determine if the received command is a continuous operation command. The command interface outputs a command signal corresponding to the command and at least one flag signal that indicates a continuous operation section if the command is a continuous operation command. A control unit is configured to receive the command signal and the at least one flag signal output from the command interface, and to generate a pump control signal based on the received command signal and the at least one flag signal. A charge pump is configured to generate a voltage in response to the pump control signal for use in accessing the memory cell array to read write and/or erase data.Type: GrantFiled: November 30, 2006Date of Patent: March 24, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Taek Jeong, Sang-Chul Kang
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Patent number: 7487082Abstract: Generating a transfer dictionary used in a transfer-based translation machine system. A pair of source/target language sentences are received. The source language sentence comprises at least one marked idiom, at least one argument and at least one marked collocation. The target language sentence comprises the target language translation for the idiom and the source language word(s) for the argument. The source language sentence is parsed to generate a source language syntactic tree. Nodes are extracted from the source language syntactic tree. A least common ancestor node of the extracted nodes is calculated and source language structure information is generated based on the source language syntactic tree data structure. Target language structure information is generated by adding the part-of-speech information to each morpheme in the target language sentence and by replacing each source language word in the target language with the corresponding syntactic information within the source language syntactic tree.Type: GrantFiled: December 3, 2007Date of Patent: February 3, 2009Assignee: International Business Machines CorporationInventors: Seong Mook Kim, Chang Woo Min, Sang Chul Kang, Jeong In Cha
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Publication number: 20080310226Abstract: Multi-bit flash memory devices are provided. The multi-bit flash memory device includes an array of memory cells and a page buffer block including page buffers. Each of the page buffers has a single latch structure and performs a write operation with respect to memory cells according to loaded data. A buffer random access memory (RAM) is configured to store program data provided from an external host device during a multi-bit program operation. Control logic is provided that is configured to control the page buffer block and the buffer RAM so that program data stored in the buffer RAM is reloaded into the page buffer block whenever data programmed before the multi-bit program operation is compared with data to be currently programmed. The control logic is configured to store data to be programmed next in the buffer RAM before the multi-bit program operation is completed.Type: ApplicationFiled: July 30, 2008Publication date: December 18, 2008Inventors: Sang-Chul Kang, Ho-Kil Lee, Jin-Yub Lee
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Patent number: 7453713Abstract: The present invention is directed to a dual chip package that is connected to a host and includes a first memory chip and a second memory chip. Each of the first and second memory chips includes a flash memory; an option pad connected to either a first or second voltage; a register configured to store a flag signal indicating whether a memory chip is selected; a comparator circuit configured to compare a flag signal stored in the register with a logic value apparent at the option pad to generate a flash access signal. Each of the first and second memory chips also includes a memory controller unit configured to access the flash memory in response to the flash access signal, and an interrupt controller unit configured to provide an interrupt signal to the host in response to the flash access signal and a control signal provided from the host.Type: GrantFiled: February 1, 2007Date of Patent: November 18, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-Min Kim, Sang-Chul Kang, Jin-Yub Lee
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Publication number: 20080144381Abstract: According to an example embodiment, a method of changing a block size in a flash memory device having a multi-plane scheme may include decoding an external input address and changing the block size of the flash memory device from a first block size to a second block size. The external input address may be decoded into a block address and a page address. The block size of the flash memory device may be changed from the first block size to the second block size by shifting at least one bit of the block address to the page address or shifting at least one bit of the page address to the block address.Type: ApplicationFiled: October 30, 2007Publication date: June 19, 2008Inventors: Sang-chul Kang, Jin-yub Lee
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Publication number: 20080084779Abstract: A semiconductor device includes a memory cell array and a command interface that is configured to receive a command from outside of the semiconductor memory device. The command interface is further configured to interpret the received command and to determine if the received command is a continuous operation command. The command interface outputs a command signal corresponding to the command and at least one flag signal that indicates a continuous operation section if the command is a continuous operation command. A control unit is configured to receive the command signal and the at least one flag signal output from the command interface, and to generate a pump control signal based on the received command signal and the at least one flag signal. A charge pump is configured to generate a voltage in response to the pump control signal for use in accessing the memory cell array to read right and/or erase data.Type: ApplicationFiled: November 30, 2006Publication date: April 10, 2008Inventors: Yong-Taek Jeong, Sang-Chul Kang
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Publication number: 20080068886Abstract: Methods of executing a multi-page copyback program in a non-volatile memory device are provided, where the non-volatile memory device includes a memory having a plurality of memory blocks. A page of data of the memory block having a first address is replaced responsive to a generated multi-page copyback program command. It is determined if the first address of the page of data is the same as a stored address of the page at which the failure was detected. The first address is incremented if it is determined that the first address and the stored address are not the same. The pages of data are replaced, the addressed are compared and the addresses are incremented until it is determined that the incremented address and the stored address are the same. Related devices and systems are also provided herein.Type: ApplicationFiled: August 23, 2007Publication date: March 20, 2008Inventors: Sang Chul Kang, Yong-Taek Jeong