Abstract: A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase in thickness of the extrinsic base provides a less resistive layer of the heavily doped base region. The method of forming the bipolar transistor includes depositing a first epitaxial layer on a substrate to form a base region having an intrinsic base region and an extrinsic base region. The extrinsic base region is raised by depositing a second epitaxial layer over a portion of the first epitaxial layer such that the thickness of the extrinsic base layer is x and the thickness of the intrinsic layer is y, wherein x>y. The second epitaxial layer is deposited using a chemical vapor epitaxial device where the concentration of Ge to Si is gradually reduced from above 5% to close to 0% during the epitaxy process.

Abstract: A method of removing a sacrificial emitter feature in a bipolar complementary metal oxide semiconductor (BICMOS) process with a super self-aligned bipolar junction transistor (BJT) is disclosed. According to the new method, a mask layer, such as an oxide deposited using high density plasma (HDP) techniques, is deposited over an extrinsic base layer and over a sacrificial emitter structure. Because of the particular characteristic of the HDP oxide, the deposition of HDP oxide forms a triangular-like structure over the sacrificial emitter structure having a maximum thickness less than the thickness of the HDP oxide over the extrinsic base layer. This facilitates the complete removal of the HDP oxide above the sacrificial emitter layer without the complete removal of the HDP oxide above the extrinsic base layer. This allows the removal of the sacrificial emitter structure while the remaining HDP oxide, serving as a mask, protects the underlying extrinsic base layer.

Abstract: A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase in thickness of the extrinsic base provides a less resistive layer of the heavily doped base region. The method of forming the bipolar transistor includes depositing a first epitaxial layer on a substrate to form a base region having an intrinsic base region and an extrinsic base region. The extrinsic base region is raised by depositing a second epitaxial layer over a portion of the first epitaxial layer such that the thickness of the extrinsic base layer is x and the thickness of the intrinsic layer is y, wherein x>y. The second epitaxial layer is deposited using a chemical vapor epitaxial device where the concentration of Ge to Si is gradually reduced from above 5% to close to 0% during the epitaxy process.

Abstract: A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase in thickness of the extrinsic base provides a less resistive layer of the heavily doped base region. The method of forming the bipolar transistor includes depositing a first epitaxial layer on a substrate to form a base region having an intrinsic base region and an extrinsic base region. The extrinsic base region is raised by depositing a second epitaxial layer over a portion of the first epitaxial layer such that the thickness of the extrinsic base layer is x and the thickness of the intrinsic layer is y, wherein x>y. The second epitaxial layer is deposited using a chemical vapor epitaxial device where the concentration of Ge to Si is gradually reduced from above 5% to close to 0% during the epitaxy process.

Abstract: A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase in thickness of the extrinsic base provides a less resistive layer of the heavily doped base region. The method of forming the bipolar transistor includes depositing a first epitaxial layer on a substrate to form a base region having an intrinsic base region and an extrinsic base region. The extrinsic base region is raised by depositing a second epitaxial layer over a portion of the first epitaxial layer such that the thickness of the extrinsic base layer is x and the thickness of the intrinsic layer is y, wherein x>y. The second epitaxial layer is deposited using a chemical vapor epitaxial device where the concentration of Ge to Si is gradually reduced from above 5% to close to 0% during the epitaxy process.

Abstract: A method for fabricating a metal oxide semiconductor field effect transistor, capable of achieving a reduction in topology by forming a trench on a silicon substrate by use of a temporary field oxide film and forming a gate electrode in the trench and capable of eliminating occurrence of a spiking phenomenon due to a metal wiring being in direct contact with the silicon substrate by forming a silicide film on a source and a drain, and capable of obtaining an increased contact margin of the metal wiring by overlapping the silicide film with a field oxide film formed on the silicon substrate.

Abstract: A metal oxide semiconductor field effect transistor having an increased channel length in a limited area of a highly integrated chip where a gate electrode is formed, and a method for fabricating the transistor. The transistor includes a semiconductor substrate having a protruded structure at a predetermined portion thereof, a gate oxide film surrounding the protruded structure of the semiconductor substrate, a polysilicon layer pattern for a gate electrode, the polysilicon layer pattern disposed over the gate oxide film, lightly doped drain regions formed in the semiconductor substrate respectively at opposite edges of the polysilicon layer pattern, and source and drain regions formed outward of the lightly doped drain regions in the semiconductor substrate respectively.

Abstract: The present invention discloses a method of forming a field oxide film in a semiconductor device which can minimize an occurrence of a birds beak by forming a pad polysilicon film between a nitride film and a pad oxide film, defining field regions by patterning the nitride film, and forming an oxidization prevention layer by implanting nitrogen atoms into portions where the bird's beak will otherwise occur.

Abstract: The present invention discloses a method of forming a field oxide film of a semiconductor device which can minimize a bird's beak by etching a predetermined portion of a silicon substrate, forming a field oxide film and forming a single crystal silicon layer on the etched silicon substrate.

Abstract: A method for fabricating a capacitor of a dynamic random access memory, capable of achieving a very high integration degree and yet obtaining a sufficient capacitance.

Abstract: There is disclosed a method for the fabrication of semiconductor device. A problem of short circuit that a metal wiring comes into contact with an area of a silicon substrate which area, when a contact hole is formed, is exposed due to misalignment of the metal wiring mask can be prevented by formation of an oxide layer in a lower area of the contact hole.

Abstract: A metal oxide semiconductor field effect transistor having an increased channel length in a limited area of a highly integrated chip where a gate electrode is formed, and a method for fabricating the transistor. The transistor includes a semiconductor substrate having a protruded structure at a predetermined portion thereof, a gate oxide film surrounding the protruded structure of the semiconductor substrate, a polysilicon layer pattern for a gate electrode, the polysilicon layer pattern disposed over the gate oxide film, lightly doped drain regions formed in the semiconductor substrate respectively at opposite edges of the polysilicon layer pattern, and source and drain regions formed outward of the lightly doped drain regions in the semiconductor substrate respectively.

Abstract: A method for forming a metal interconnection capable of minimizing plasma etching damage on a metal layer having a relatively higher step when forming a via hole.

Abstract: A method of forming a capacitor in a semiconductor device is disclosed. A charge storage electrode is formed with a third polysilicon layer connected to a fourth polysilicon layer. A dielectric layer is formed with a first dielectric layer connected to a second dielectric layer. A plate electrode is formed by connecting the first polysilicon layer to the sixth polysilicon layer. The first polysilicon layer is formed under the third polysilicon layer. The first dielectric layer is formed between the first polysilicon layer and the third polysilicon layer.

Abstract: A method for manufacturing a transistor of a semiconductor device having a gate electrode smaller than the critical dimensions of a mask for a gate electrode by etching a polysilicon film for a gate electrode using an isotropic etching process and an anisotropic etching process utilizing a mask layer by forming the mask layer on the top of the polysilicon film for a gate electrode. This allows forming a gate electrode smaller than the critical dimensions by utilizing the prior art exposing apparatus; therefore, production costs for manufacturing the semiconductor can be reduced, and additionally, the manufacture of a highly integrated semiconductor device can be simplified by forming a gate electrode smaller than the critical dimensions.

Abstract: A method for the fabrication of DRAM cell is disclosed. The method is characterized by forming a trench in a field oxide in a transistor consisting of a field oxide, a gate insulating layer, a gate electrode capped with an insulating layer, a spacer insulating film and an impurity ion-implanted region connected with a capacitor. The trench formed in a field oxide effects an increase in a surface area of the charge storage electrode, resulting in an increased capacitance. Therefore, the method disclosed can overcome the limit of the conventional stacked capacitor which increases its surface area by heightening the charge storage electrode, maximizing charge storage capacitance. Consequently, the method can effect a high degree of integration in manufacturing a semiconductor device.

Abstract: A method for forming a field oxide film in a semiconductor device comprises the steps of sequentially forming a pad oxide film and a first buffer silicon nitride film on a silicon substrate, and then forming a first patterned mask on the first buffer silicon nitride film. Subsequently, the resulting exposed part of the first buffer silicon nitride film is etched to expose a portion of the pad oxide film. The first patterned mask is them removed. A buffer oxide film is formed on the resulting exposed part of the pad oxide film and the etched first buffer silicon nitride film. Then, a second buffer silicon nitride film and a second patterned mask is sequentially formed on the buffer oxide film, followed by etching of the resulting exposed part of the second buffer silicon nitride. The second patterned mask is then removed, followed by a formation of a field oxide film by thermal oxidation on the resulting structure. The second buffer silicon nitride is then removed.

Abstract: A rotary-type wafer drying apparatus includes a deflection prevention protecting plate attached to a cradle for a wafer, for diminishing rebounding of dewaterized water. A free side of the protecting plate in the cradle containing wafer maintains an appropriate angle with the cradle and the transverse length of the plate is longer than the transverse length of the radially outward side of the cradle.

Abstract: A method for insulating a polysilicon film in a semiconductor device is disclosed.The method comprises the steps of: forming a trench in a semiconductor covered with a first oxide film, a buffing polysilicon film and a nitride film in due order, with a mask pattern for forming the trench; coating the trench with an insulating film and filling the resulting trench with a polysilicon film for forming charge storage electrode; oxidizing the surface of the polysilicon to form a second oxide film on the polysilicon film; and implanting silicon atoms in the polysilicon film through the second oxide film to make a predetermined, upper portion of the polysilicon film be amorphous.The thickness difference of the oxide film formed on the polysilicon film of the trench is minimized by use of the buffing polysilicon film according to the present invention.

Abstract: It is a process for producing trimellitic acid (trimellitic acid, 1, 2, 4-tricarboxylic acid) by oxidizing pseudocumene with a molecular oxygen containing gas. More particularly, pseudocumene is oxidized into trimellitic acid by introducing a molecular oxygen containing gas in an acetic acid solvent in the presence of oxidizing catalysts, wherein the oxidization reactions in two different stages which have different ranges of temperature and different compositions of catalyst, respectively.