Abstract: A deflection yoke includes a vertical deflection coil part and first and second pairs of coils that are symmetrically disposed around a portion of the vertical deflection coil part. Winding directions of the first pair of coils are opposite to those of the second pair of coils, thereby compensating for the misconvergence incurred when light spot is vertically displaced.

Abstract: An electronic directory of phone numbers, a mobile terminal having the same, and a management method thereof. The electronic directory of phone numbers includes a plurality of graphic icons; and a plurality of phone numbers respectively linked to the plurality of graphic icons. The plurality of graphic icons form a graphic map. The graphic map includes a community configured by the icons. Each of the icons is updated according to a call history based on a phone number mapped thereto.

Abstract: A power-shifted transmission for industrial vehicles comprises a transmission casing and input and output shafts rotatably mounted on the transmission casing. The input and output shafts are drivingly connectable to each other through a forward shaft assembly, a reverse shaft assembly and an intermediate shaft assembly. The forward shaft assembly is rotatingly driven by the input shaft and operable to deliver the torque of the input shaft to the output shaft at a first or second forward gear ratio. The reverse shaft assembly is rotatingly driven by the forward shaft assembly and operable to deliver the torque of the input shaft to the output shaft at a first or second reverse gear ratio. The intermediate shaft assembly is rotatingly driven by the reverse shaft assembly and operable to deliver the torque of the input shaft to the output shaft at a third forward gear ratio.

Abstract: A memory device with skew-reducible memory cell arrangement, comprising a memory cell array being divided into a plurality of cell regions; a sense-amplifying means being comprised of a plurality of a first sense amplifiers disposed in the upper side of the memory cell and a plurality of second sense amplifiers disposed in the lower side of the memory cell array; a plurality of bit line pairs, each of bit line pairs being connected to the respective sense amplifiers and being divided into a plurality of bit line segment pairs; a connection means for connecting or disconnecting the bit line segment pairs to the sense amplifiers in accordance with a plurality of control signal pairs; and a control circuit for receiving a plurality of cell region selection signals for selecting corresponding one of the plurality of cell regions to generate the plurality of control signal pairs to the connection means.

Abstract: A high voltage generator generates a high voltage higher than a power-supply voltage by a predetermined potential in order to supplement a loss of a threshold potential of a transistor in a semiconductor memory device. The high voltage generator has each potential sensing unit for a standby mode and active mode. In case of the standby mode, the high voltage generator minimizes a current consumption, and stably generates a high voltage. In case of the active mode, the high voltage generator limits a potential variation width of high voltage, thereby stably generating a high voltage at a high-speed.

Abstract: A word line driver in a semiconductor memory device. The driver has first to (2.sup.m-n)th middle decoding units for commonly inputting an address signal of n bit and for outputting metal control signals by 2.sup.n so as to selectively drive 2.sup.m word lines by dividing them by 2.sup.n ; a main decoding unit for selectively driving the first to (m-n)bits th middle decoding units by an address signal of (m-n) bits; and first to (2.sup.m-n)th sub decoding units for commonly inputting a high voltage via a metal power line, and after coupled with 2.sup.n word lines of the 2.sup.m word lines of the cell array block, for selectively applying the high voltage to the 2.sup.n word lines to selectively drive them according to logic signals of 2.sup.n metal control lines, the first to (2.sup.m-n)th sub decoding units being coupled with the first to (2.sup.m-n)th middle decoding units and the 2.sup.n metal control lines, respectively.