Patents by Inventor Sang-Hoon Hong
Sang-Hoon Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20110085405Abstract: A semiconductor memory device includes a row decoding block for decoding an inputted address to thereby generate a logical unit cell block address and a decoded word line address; a tag block for converting the logical unit cell block address into a physical unit cell block address; a decoded address latching block for latching the decoded word line address to thereby output the decoded word line address as a word line activation signal in response to the physical unit cell block; and a cell area for outputting a data, which is stored therein, in response to the word line activation signal.Type: ApplicationFiled: December 15, 2010Publication date: April 14, 2011Inventors: Sang-Hoon Hong, Jin-Hong Ahn, Jae-Bum Ko, Se-Jun Kim
-
Patent number: 7870362Abstract: A semiconductor memory device includes a row decoding block for decoding an inputted address to thereby generate a logical unit cell block address and a decoded word line address; a tag block for converting the logical unit cell block address into a physical unit cell block address; a decoded address latching block for latching the decoded word line address to thereby output the decoded word line address as a word line activation signal in response to the physical unit cell block; and a cell area for outputting a data, which is stored therein, in response to the word line activation signal.Type: GrantFiled: June 28, 2004Date of Patent: January 11, 2011Assignee: Hynix Semiconductor Inc.Inventors: Sang-Hoon Hong, Jin-Hong Ahn, Jae-Bum Ko, Se-Jun Kim
-
Patent number: 7679970Abstract: Disclosed herein is a semiconductor memory device which can simultaneously perform a read access and a write access independently. The semiconductor memory device according to the present invention can access a plurality of data through the global sense amplifying unit and the global bit line, and enables the read controller and the write controller to independently control the global bit line and the bit line sense amplifying unit to be connected to each other to thereby perform the read access and the write access simultaneously.Type: GrantFiled: March 31, 2008Date of Patent: March 16, 2010Assignee: University-Industry Cooperation Group of Kyung Hee UniversityInventor: Sang Hoon Hong
-
Publication number: 20080259692Abstract: Disclosed herein is a semiconductor memory device which can simultaneously perform a read access and a write access independently. The semiconductor memory device according to the present invention can access a plurality of data through the global sense amplifying unit and the global bit line, and enables the read controller and the write controller to independently control the global bit line and the bit line sense amplifying unit to be connected to each other to thereby perform the read access and the write access simultaneously.Type: ApplicationFiled: March 31, 2008Publication date: October 23, 2008Applicant: University-Industry Cooperation Group of Kyung Hee UniversityInventor: Sang Hoon Hong
-
Patent number: 7363460Abstract: A memory device includes a cell area having N+1 unit cell blocks. Each cell block includes M word lines. The N unit cell blocks are each corresponded to a logical cell block address. The one additional unit cell block is added for accessing data with high speed. A tag block receives a row address, senses the logical cell block address in the row address and outputs a physical cell block address based on the logical cell block address and the candidate information. The tag block includes:N+1 unit tag tables corresponding to the N+l unit cell blocks. Each tag block has M number of registers. The M number of registers correspond to M number of word lines of the corresponding unit cell blocks. Each register stores one logical cell block address. The tag block also includes an initialization unit that initializes the N+1 unit tag tables.Type: GrantFiled: December 30, 2003Date of Patent: April 22, 2008Assignee: Hynix Semiconductor Inc.Inventors: Jae-Bum Ko, Jin-Hong Ahn, Sang-Hoon Hong, Se-Jun Kim
-
Patent number: 7304877Abstract: A semiconductor memory device includes: a core region having a plurality of bank sets for outputting/storing a data in response to an inputted address, wherein each bank set includes one bank, one row address control unit and two column address control units; and a peripheral region having two pad groups, wherein two pad groups are respectively located at the opposite side of the core region.Type: GrantFiled: December 29, 2004Date of Patent: December 4, 2007Assignee: Hynix Semiconductor Inc.Inventors: Jae-Bum Ko, Sang-Hoon Hong, Se-Jun Kim
-
Patent number: 7277977Abstract: A DRAM with a general interleaving scheme for data input/output uses a normal bank structure. The DRAM provides a high-performance without consideration of a data access pattern. In order to implement the high-performance, the DRAM includes a plurality of normal banks, at least one cache bank, which has the same data access scheme with the normal banks, for selectively storing data with a normal bank selected at a read mode and a controller for controlling the access to the cache bank and the selected normal bank when continuous read commands are occurred to the selected normal bank.Type: GrantFiled: December 30, 2002Date of Patent: October 2, 2007Assignee: Hynix Semiconductor Inc.Inventors: Jeong-Hoon Kook, Sang-Hoon Hong, Se-Jun Kim
-
Patent number: 7224609Abstract: A unit cell included in a non-volatile dynamic random access memory (NVDRAM) includes a control gate layer coupled to a word line; a capacitor for storing data; a floating transistor for transmitting stored data in the capacitor to a bit line, gate of the floating transistor being a single layer and serving as a temporary data storage; and a first insulating layer between the control gate layer and the gate of the floating transistor, wherein a voltage supplied to body of the floating transistor is controllable.Type: GrantFiled: November 21, 2005Date of Patent: May 29, 2007Assignee: Hynix Semiconductor Inc.Inventors: Jin-Hong Ahn, Sang-Hoon Hong, Young-June Park, Sang-Don Lee, Yil-Wook Kim, Gi-Hyun Bae
-
Patent number: 7174418Abstract: A semiconductor device for refreshing data stored in a memory device includes a cell area having N+1 number of unit cell blocks, each including M number of word lines which respectively are coupled to a plurality of unit cells; a tag block having N+1 number of unit tag blocks, each storing at least one physical cell block address denoting a row address storing a data; and a control block for controlling the tag block and the predetermined cell block table for refreshing the data in the plurality of unit cells coupled to a word line in response to the physical cell block address.Type: GrantFiled: December 30, 2003Date of Patent: February 6, 2007Assignee: Hynix Semiconductor Inc.Inventors: Sang-Hoon Hong, Jin-Hong Ahn, Jae-Bum Ko, Se-Jun Kim
-
Patent number: 7099181Abstract: A method for operating a non-volatile dynamic random access memory (NVDRAM) device having a plurality of memory cells, each cell having a capacitor and a transistor having a floating gate includes the steps of (A) preparing a power-on mode for performing a DRAM operation; and (B) preparing a power-off mode for holding stored data in the memory cell.Type: GrantFiled: December 31, 2003Date of Patent: August 29, 2006Assignee: Hynix Semiconductor Inc.Inventors: Jin-Hong Ahn, Sang-Hoon Hong, Young-June Park, Sang-Don Lee, Yil-Wook Kim, Gi-Hyun Bae
-
Patent number: 7088637Abstract: A semiconductor memory device having a high speed for a data transmission includes a plurality of cell blocks, each having a plurality of unit cells for storing data; a plurality of local bit line sense amplifying block, each for sensing and amplifying the data stored in the N number of cell blocks; a global bit line sense amplifying block for latching the data amplified by the local bit line sense amplifying blocks; and a data transferring block for transmitting the data from the local bit line sense amplifying block to the global bit line sense amplifying block.Type: GrantFiled: June 25, 2004Date of Patent: August 8, 2006Assignee: Hynix Semiconductor, Inc.Inventors: Jae-Bum Ko, Jin-Hong Ahn, Sang-Hoon Hong, Se-Jun Kim
-
Patent number: 7078949Abstract: An analog delay locked loop device includes a first block for receiving an internal clock signal and a reference clock signal to generate normal multi phase clock signal pairs and dummy multi phase clock signal pairs; and a second block for receiving the reference clock signal to generate a delay locked internal clock signal having a corrected duty cycle based on the normal multi phase clock signal pairs and the dummy multi phase clock signal pairs.Type: GrantFiled: December 31, 2003Date of Patent: July 18, 2006Assignee: Hynix Semiconductor Inc.Inventors: Se-Jun Kim, Sang-Hoon Hong, Jae-Bum Ko
-
Patent number: 7075847Abstract: An apparatus for controlling a refresh cycle in a semiconductor memory device includes a temperature detection controller for generating a detection control signal and a converting control signal; a temperature detection block, which is enabled by the detection control signal, for generating an analog detection voltage in response to a temperature variation; an analog to digital converter, which is enabled by the converting control signal, for converting the analog detection voltage into a digital control code; and a refresh controller for generating a refresh cycle control signal based on the digital control code in order to control the refresh cycle.Type: GrantFiled: June 23, 2004Date of Patent: July 11, 2006Assignee: Hynix Semiconductor Inc.Inventors: Se-Jun Kim, Sang-Hoon Hong, Jae-Bum Ko
-
Patent number: 7068561Abstract: A semiconductor memory device for an effective data access operation includes a cell area having N+1 number of unit cell blocks, each including M number of word lines, for storing a data in a unit cell corresponding to an inputted address; N+1 number of unit controlling blocks having respective state machines and corresponding to the respective N+1 unit cell blocks for controlling a data restoration that is accessed from a first unit cell block selected from the N+1 unit cell blocks into the first unit cell block or a second unit cell block; and a driving controlling block for controlling the N+1 unit cell blocks so that the N+1 unit controlling means are in one of first to fourth operation states.Type: GrantFiled: December 20, 2004Date of Patent: June 27, 2006Assignee: Hynix Semiconductor Inc.Inventors: Sang-Hoon Hong, Jae-Bum Ko, Se-Jun Kim
-
Patent number: 7057964Abstract: A semiconductor memory device includes: a memory core area; a plurality of address input pads for transferring addresses; a first address buffer part for receiving the addresses and outputting first addresses; a plurality of multi I/O pads for inputting/outputting data or inputting/outputting addresses/data while multiplexing the addresses/data; a data I/O buffer part for receiving data from the plurality of multi I/O pads and transferring the data to the memory core area or receiving and outputting addresses; a second address buffer part for receiving the addresses from the data I/O buffer part and outputting second addresses; an address multiplexer part for combining the first addresses and the second addresses and outputting data access addresses to the memory core area; and a path control part for controlling the address multiplexer part.Type: GrantFiled: December 20, 2004Date of Patent: June 6, 2006Assignee: Hynix Semiconductor Inc.Inventors: Sang-Hoon Hong, Jae-Bum Ko, Se-Jun Kim
-
Patent number: 7054201Abstract: A driving circuit for use in a non-volatile dynamic random access memory (NVDRAM) having a nonconductor which can trap electrons or holes includes an internal supply voltage generator for generating the plurality of internal supply voltages, each having at least two different voltage levels; a mode controller for determining an operation mode of the NVDRAM; a voltage level selector for selecting one voltage level of each internal supply voltage in response to the operation mode to thereby outputs the selected voltage level of each internal supply voltage to the row decoding block and the core area; a row decoding block for receiving the internal supply voltages and outputting the internal supply voltages in response to an inputted address; and a core area having a plurality of unit cells, each storing a data, for accessing the data in response to inputted voltage levels of the plurality of internal supply voltages.Type: GrantFiled: June 30, 2004Date of Patent: May 30, 2006Assignee: Hynix Semiconductor Inc.Inventors: Jin-Hong Ahn, Sang-Hoon Hong, Sang-Don Lee, Yil-Wook Kim, Young-Jun Park
-
Publication number: 20060083068Abstract: A unit cell included in a non-volatile dynamic random access memory (NVDRAM) includes a control gate layer coupled to a word line; a capacitor for storing data; a floating transistor for transmitting stored data in the capacitor to a bit line, gate of the floating transistor being a single layer and serving as a temporary data storage; and a first insulating layer between the control gate layer and the gate of the floating transistor, wherein a voltage supplied to body of the floating transistor is controllable.Type: ApplicationFiled: November 21, 2005Publication date: April 20, 2006Inventors: Jin-Hong Ahn, Sang-Hoon Hong, Young-June Park, Sang-Don Lee, Yil-Wook Kim, Gi-Hyun Bae
-
Patent number: 6996007Abstract: A unit cell included in a non-volatile dynamic random access memory (NVDRAM) includes a control gate layer coupled to a word line; a capacitor for storing data; a floating transistor for transmitting stored data in the capacitor to a bit line, gate of the floating transistor being a single layer and serving as a temporary data storage; and a first insulating layer between the control gate layer and the gate of the floating transistor, wherein a voltage supplied to body of the floating transistor is controllable.Type: GrantFiled: December 31, 2003Date of Patent: February 7, 2006Assignee: Hynix Semiconductor, Inc.Inventors: Jin-Hong Ahn, Sang-Hoon Hong, Young-June Park, Sang-Don Lee, Yil-Wook Kim, Gi-Hyun Bae
-
Patent number: 6987409Abstract: An analog DLL device includes a delay model for modeling delay time for buffering the external clock signal; a phase comparator for comparing a phase of the reference clock signal with an phase of an outputted signal from the delay model; a charge pump for pumping charges; a loop filter for generating a reference voltage; a voltage control delay line and a tracking digital-analog converter which converts the reference voltage to a digital value; and stores the digital value for keeping the reference voltage safely.Type: GrantFiled: December 31, 2003Date of Patent: January 17, 2006Assignee: Hynix Semiconductor Inc.Inventors: Se-Jun Kim, Sang-Hoon Hong, Jae-Bum Ko
-
Patent number: 6937535Abstract: A memory device includes at least two cell blocks connected to a global bit line for outputting data in response to an instruction; at least one global bit line connection unit for selectively connecting the global bit line to each cell block under control of a control block, one global bit line connection unit being allocated between the two cell blocks; and said control block for controlling output of data stored in each cell block to the global bit line and restoration of the outputted data of the global bit line to the original cell block or another cell block which is determined by depending upon whether data in response to a next instruction is outputted from the original cell block or another cell block.Type: GrantFiled: October 28, 2003Date of Patent: August 30, 2005Assignee: Hynix Semiconductor Inc.Inventors: Jin-Hong Ahn, Sang-Hoon Hong, Se-Jun Kim, Jae-Bum Ko