Abstract: The present disclosure provides a seat cushion extension device for a fold-and-dive seat. The seat cushion extension device may include a pair of seat cushion side frames arranged at a predetermined interval, a seatback frame rotatably connected to the pair of seat cushion side frames and having a guide pin formed on an outer surface thereof, a seat cushion frame, a pair of links rotatably connected between the pair of seat cushion side frames and a front end of the seat cushion frame, and a pair of extension frames. Each of the pair of extension frames may have a front end connected to the seat cushion frame, and a rear end formed with a guide hole, into which a guide pin may be inserted. The seat cushion extension device may facilitate a forward extension of a seat cushion regardless of a position of a seatback of the fold-and-dive seat.

Abstract: A memory device includes a cell array including cells, an address transition detector outputting a transition detection signal as to whether an address of a write command is changed, and a control logic circuit generating one of word-line-on signals for performing a write operation on the cell array in response to the write command, and terminating the write operation in accordance with the transition detection signal. The word-line-on signals include a long-kept word-line-on signal that stays active before the address is changed and a divided word-line-on signal that is, before the address is changed, divided into sub-word-line-on signals.

Abstract: In the present specification, on the basis of the correlation between prospero homeobox protein 1 (PROX1) and telomerase reverse transcriptase (TERT), a composition for regulating expression of TERT, a method for screening a TERT expression regulator, a composition for diagnosing a TERT expression status, a diagnostic kit, a method for providing information for diagnosis, or a method for providing information for cancer diagnosis are disclosed. Specifically, in one aspect, the PROX1 of the present disclosure may bind to a TERT promoter, in particular a mutant TERT promoter in which base substitution occurs at the -124 or -146 bp position to regulate the expression of TERT, and the expression of TERT in non-hepatitis B virus-associated liver cancer can be inhibited specifically among liver cancers.

Abstract: A memory device is provided. The memory device includes a plurality of memory chips that are stacked, wherein each of the memory chips includes a memory cell array, which includes a plurality of memory cell rows, a chip identifier generator configured to generate a chip identifier signal indicating a chip identifier of each of the memory chips, a refresh counter configured to generate a target row address for refreshing the memory cell rows in response to a refresh command, and a target row address generator, which receives the chip identifier signal and the target row address and outputs one of the target row address and an inverted target row address, obtained by inverting the target row address, as a refresh row address based on the chip identifier signal, and performs a refresh operation on a memory cell row corresponding to the refresh row address.

Abstract: Magnetic junction memory devices and methods for writing data to memory devices are provided. The magnetic junction memory device includes a first memory bank including first magnetic junction memory cells, a first local write driver adjacent to the first memory bank, connected to global data lines, the first local write driver configured to write data to the first magnetic junction memory cells via local data lines, a second memory bank adjacent to the first memory bank and including second magnetic junction memory cells, a second local write driver adjacent to the second memory bank, connected to the global data lines, the second local write driver configured to write data to the second magnetic junction memory cells via local data lines, and a global write driver configured to provide first and second write data to the first and second local write driver, respectively, via the global data lines.

Abstract: The present invention relates to a device for measuring a bodily fluid drainage amount, the device comprising: a measurement case which is formed of a rigid material and provided with a bodily fluid measurement space therein; a drainage tube which is coupled to an entrance of the measurement case in a releasable structure and transfers bodily fluids discharged from a human body to the bodily fluid measurement space of the measurement case; a plurality of fluid level sensors, which are horizontally disposed on an upper surface of the measurement case and measure and inform fluid levels of the bodily fluids collected in the bodily fluid measurement space; and a control device which receives and analyzes the fluid levels of the bodily fluids, infers a tilt of the measurement case from a difference in the fluid levels of the bodily fluids, and calculates and informs a bodily fluid drainage amount.

Abstract: Magnetic junction memory devices and methods for writing data to memory devices are provided. The magnetic junction memory device includes a first memory bank including first magnetic junction memory cells, a first local write driver adjacent to the first memory bank, connected to global data lines, the first local write driver configured to write data to the first magnetic junction memory cells via local data lines, a second memory bank adjacent to the first memory bank and including second magnetic junction memory cells, a second local write driver adjacent to the second memory bank, connected to the global data lines, the second local write driver configured to write data to the second magnetic junction memory cells via local data lines, and a global write driver configured to provide first and second write data to the first and second local write driver, respectively, via the global data lines.

Abstract: A memory device includes a cell array including cells, an address transition detector outputting a transition detection signal as to whether an address of a write command is changed, and a control logic circuit generating one of word-line-on signals for performing a write operation on the cell array in response to the write command, and terminating the write operation in accordance with the transition detection signal. The word-line-on signals include a long-kept word-line-on signal that stays active before the address is changed and a divided word-line-on signal that is, before the address is changed, divided into sub-word-line-on signals.

Abstract: A memory device includes a cell array including cells, an address transition detector outputting a transition detection signal as to whether an address of a write command is changed, and a control logic circuit generating one of word-line-on signals for performing a write operation on the cell array in response to the write command, and terminating the write operation in accordance with the transition detection signal. The word-line-on signals include a long-kept word-line-on signal that stays active before the address is changed and a divided word-line-on signal that is, before the address is changed, divided into sub-word-line-on signals.

Abstract: Provided are a die pickup module and a die bonding apparatus including the same. The die pickup module includes a wafer stage for supporting a wafer including dies attached on a dicing tape, a die ejector arranged under the dicing tape and for separating a die to be picked up from the dicing tape, a non-contact picker for picking up the die in a non-contact manner so as not to contact a front surface of the die, a vertical driving unit for moving the non-contact picker in a vertical direction to pick up the die and an inverting driving unit for inverting the non-contact picker to invert a die picked up by the non-contact picker.

Abstract: Magnetic junction memory devices and methods for writing data to memory devices are provided. The magnetic junction memory device includes a first memory bank including first magnetic junction memory cells, a first local write driver adjacent to the first memory bank, connected to global data lines, the first local write driver configured to write data to the first magnetic junction memory cells via local data lines, a second memory bank adjacent to the first memory bank and including second magnetic junction memory cells, a second local write driver adjacent to the second memory bank, connected to the global data lines, the second local write driver configured to write data to the second magnetic junction memory cells via local data lines, and a global write driver configured to provide first and second write data to the first and second local write driver, respectively, via the global data lines.

Abstract: A memory device includes a first memory cell that is connected with a first source line, a first word line, and a first bit line, a first write circuit to receive first write data that are stored in the first memory cell through a first write input/output line and to control a voltage of the first source line and a voltage of the first bit line based on the first write data, and a first pull-down circuit to receive first pull-down data corresponding to the first write data from the first write circuit through a first internal metal line and to pulls down the voltage of at least one of the first source line and the first bit line to a predetermined voltage based on the first pull-down data.

Abstract: A memory device includes a cell array including cells, an address transition detector outputting a transition detection signal as to whether an address of a write command is changed, and a control logic circuit generating one of word-line-on signals for performing a write operation on the cell array in response to the write command, and terminating the write operation in accordance with the transition detection signal. The word-line-on signals include a long-kept word-line-on signal that stays active before the address is changed and a divided word-line-on signal that is, before the address is changed, divided into sub-word-line-on signals.

Abstract: Provided is an apparatus that can check in real time a process of removing light induced degradation using precise carrier injection through an AC power supply device (power unit). An apparatus for reduction of light induced degradation with carrier injection includes: a housing in which high-temperature heat treatment is performed on a solar battery cell; a heating unit that is formed in the housing, on which the solar battery cell is seated, and that heats the solar battery cell; a jig unit that is formed in the housing and fixes the solar battery cell to the heating unit by pressing the solar battery cell seated on the heating unit; an LED array unit that has a plurality of LED light sources and radiates light to the solar battery cell; and a driving unit that is coupled to the jig unit and the LED array unit and rotates the jig unit or the LED array unit.

Abstract: A potential induced degradation test apparatus for a solar cell includes a PID test chamber (101), a mounting unit (110), one or more PID supply means of a PID test sheet (120) or a PID-causing substance supply unit (140), a heating unit (130), a voltage applying unit (150), and a PID measuring unit (160). The potential induced degradation test apparatus is capable of quantifying a level of a cell and durability against PID of individual configurational members such as an encapsulant of a solar cell module by a method of directly applying solid Na and vaporized Na ions quantified by minimum cell unit in a method in which large-area modularization of the solar cell module is not performed.

Abstract: A memory device includes a first memory cell that is connected with a first source line, a first word line, and a first bit line, a first write circuit to receive first write data that are stored in the first memory cell through a first write input/output line and to control a voltage of the first source line and a voltage of the first bit line based on the first write data, and a first pull-down circuit to receive first pull-down data corresponding to the first write data from the first write circuit through a first internal metal line and to pulls down the voltage of at least one of the first source line and the first bit line to a predetermined voltage based on the first pull-down data.

Abstract: Provided is an amine group-derivatized composition including a Boc compound for liquid chromatography-mass spectrometry (LC-MS) analysis, and when the amine group-derivatized composition is used in analysis using reverse-phase LC-MS, it is possible to effectively analyze compounds including an amine group and an amino acid at a low cost in a short time.

Abstract: Provided is an apparatus that can check in real time a process of removing light induced degradation using precise carrier injection through an AC power supply device (power unit). An apparatus for reduction of light induced degradation with carrier injection includes: a housing in which high-temperature heat treatment is performed on a solar battery cell; a heating unit that is formed in the housing, on which the solar battery cell is seated, and that heats the solar battery cell; a jig unit that is formed in the housing and fixes the solar battery cell to the heating unit by pressing the solar battery cell seated on the heating unit; an LED array unit that has a plurality of LED light sources and radiates light to the solar battery cell; and a driving unit that is coupled to the jig unit and the LED array unit and rotates the jig unit or the LED array unit.

Abstract: A memory device includes a first fail address register that stores a fail address, an input address register that stores an input address, a data comparison circuit that compares write data to be stored in a memory cell corresponding to the input address with read data read from the memory cell, an address comparison circuit that compares the fail address and the input address, and a second fail address register that stores bits of the fail address in parallel based on a first comparison result of the write data with the read data and a second comparison result of the fail address with the input address.

Abstract: A high voltage start-up circuit includes a power supply terminal configured to supply power, a latch unit connected to the power supply terminal and comprising a first P-type Metal-Oxide-Semiconductor (PMOS) transistor, a first N-type metal-oxide semiconductor (NMOS) transistor connected to the first PMOS transistor, a second PMOS transistor, and a second NMOS transistor connected to the second PMOS transistor, wherein the transistors form a latch structure, a charge sharing unit comprising a first capacitor configured to supply a first voltage to a drain of the second PMOS transistor and a second capacitor configured to supply a second voltage to a drain of the first PMOS transistor, and a switching unit configured to form a current path that charges an external capacitor using a voltage supplied from the power supply terminal as a power voltage, based on the first voltage and the second voltage.