Patents by Inventor Sang-Hyuck OH

Sang-Hyuck OH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11944661
    Abstract: The present invention provides a pharmaceutical composition for prevention or treatment of a stress disease and depression, the pharmaceutical composition be safely useable without toxicity and side effects by using an extract of leaves of Vaccinium bracteatum Thunb., which is natural resource of Korea, so that the reduction of manufacturing and production costs and the import substitution and export effects can be expected through the replacement of a raw material for preparation with a plant inhabiting in nature.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: April 2, 2024
    Assignee: JEONNAM BIOINDUSTRY FOUNDATION
    Inventors: Chul Yung Choi, Dool Ri Oh, Yu Jin Kim, Eun Jin Choi, Hyun Mi Lee, Dong Hyuck Bae, Kyo Nyeo Oh, Myung-A Jung, Ji Ae Hong, Kwang Su Kim, Hu Won Kang, Jae Yong Kim, Sang O Pan, Sung Yoon Park, Rack Seon Seong
  • Patent number: 10756044
    Abstract: A fan-out semiconductor package includes a connection member including an insulating layer, a redistribution layer, and conductive vias penetrating through the insulating layer and connected to the redistribution layer, and a semiconductor chip and a passive chip disposed on the connection member and electrically connected to the redistribution layer. A conductive via connected to the passive element among the conductive vias has a multiple via shape in which a plurality of sub-vias, a width of each sub-via is decreased in a thickness direction, and end portions of the plurality of sub-vias are integrated with each other.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: August 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sang Hyuck Oh
  • Publication number: 20190172809
    Abstract: A fan-out semiconductor package includes a connection member including an insulating layer, a redistribution layer, and conductive vias penetrating through the insulating layer and connected to the redistribution layer, and a semiconductor chip and a passive chip disposed on the connection member and electrically connected to the redistribution layer. A conductive via connected to the passive element among the conductive vias has a multiple via shape in which a plurality of sub-vias, a width of each sub-via is decreased in a thickness direction, and end portions of the plurality of sub-vias are integrated with each other.
    Type: Application
    Filed: March 30, 2018
    Publication date: June 6, 2019
    Inventor: Sang Hyuck OH
  • Publication number: 20180072972
    Abstract: Systems, devices, and methods for the automated production of fermented beverages are provided. The device may be modular, portable and/or self-cleaning. The device includes a housing with chambers that receive a removable fermentation vessel with yeasts and ingredients capable of undergoing fermentation. Flavoring agents and other ingredients may also be added to produce beer, wine, or other alcoholic libations of profound character and freshness. The device includes a controller that initiates fermentation, senses the fermentation status and automatically controls fermentation parameters based on a desired fermentation profile. The controller automatically directs parameters such as carbonation, conditioning, aging, and chilling according to a programmed recipe or consumer preference to create an enjoyable customized beverage.
    Type: Application
    Filed: September 11, 2017
    Publication date: March 15, 2018
    Applicant: Alpha Revolution, Inc.
    Inventors: Jong-Wook Shin, Yoon-Sang Kim, Sang-Hyuck Oh, Byung-Kyu Kang
  • Publication number: 20140102767
    Abstract: Disclosed herein is a multi-layer type printed circuit board, including; a first insulating layer including at least one first pillar; a plurality of insulating layers laminated in a both surfaces direction of the first insulating layer, each including at least one circuit layer and at least another pillar connected to the circuit layer; and a plurality of outermost circuit layers disposed on an outer surface of the outermost insulating layer, while contacting an outermost pillar disposed on an outermost insulating layer among the plurality of insulating layers, wherein the circuit layer and another pillar each formed in a both surfaces direction of the first insulating layer are disposed in a symmetrical form to each other based on the first insulating layer.
    Type: Application
    Filed: March 18, 2013
    Publication date: April 17, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Myung Sam Kang, Ki Hwan Kim, Yong Yoon Cho, Sung Won Jeong, Sang Hyuck Oh, Da Hee Kim, Yoong Oh, Ki Young Yoo
  • Publication number: 20140027156
    Abstract: Disclosed herein is a method of manufacturing a multilayer type coreless substrate, the method including: (A) preparing a carrier substrate including at least one copper foil formed on one surface or both surfaces of an insulating surface; (B) forming a coreless printed circuit precursor on one surface or both surfaces of the carrier substrate; (C) separating the carrier substrate; (D) performing a polishing cutting process on the coreless printed circuit precursor; and (E) laminating a plurality of other insulating layers on a flat outer surface of the coreless printed circuit precursor, the plurality of other insulating layers sequentially including other circuit layers and other pillars.
    Type: Application
    Filed: October 30, 2012
    Publication date: January 30, 2014
    Applicant: Samsung Electro-Mechanics Co., Ltd
    Inventors: Ki Hwan Kim, Myung Sam Kang, Keung Jin Sohn, Yoong Oh, Da Hee Kim, Ki Young Yoo, Han Ui Lee, Sang Hyuck Oh
  • Publication number: 20120055800
    Abstract: Disclosed herein is a method for forming a plating layer of a printed circuit board. A deviation in plating thickness of a copper plating layer filled in a circuit pattern part and a through-hole part in a SIP product group having a narrow through-hole pitch and a large through-hole volume may be reduced. To this end, there is provided a method for forming a plating layer of a printed circuit board, the method including: processing a though-hole in a copper clad lamination (CCL); forming a seed plating layer in the through hole; applying a resist on the CCL and the seed plating layer and exposing and developing the resist; forming a primary plating layer on the seed plating layer; forming a copper plating layer on the primary plating layer; and removing the resist remaining on the primary plating layer and the seed plating layer to thereby form patterns.
    Type: Application
    Filed: September 6, 2011
    Publication date: March 8, 2012
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jeong Ho MOON, Sang-Hyuck OH