Abstract: A memory system includes: a memory device suitable for performing a refresh operation in response to a refresh command, and for providing a refresh end signal where the refresh end signal is enabled before the refresh operation is completed; and a memory controller suitable for transferring the refresh command to the memory device and receiving the refresh end signal.

Abstract: A data transmission circuit may include a first driving block configured to drive an output terminal for a first time in response to a data driving signal and a level of the output terminal, and a second driving block configured to drive the output terminal for a second time after the first time, in response to the data driving signal.

Abstract: A semiconductor memory apparatus includes an effective region which is a portion of the memory region and functions as a data storage space, a residual region which is another portion of the memory region, and a capacity control circuit which restricts supply of power and signals to the residual region.

Abstract: A data transmission circuit may include a first driving block configured to drive an output terminal for a first time in response to a data driving signal and a level of the output terminal, and a second driving block configured to drive the output terminal for a second time after the first time, in response to the data driving signal.

Abstract: An operation mode setting circuit of a semiconductor apparatus includes a mode register set configured to update an operation mode information generated internally at the semiconductor apparatus based on preliminary information data in response to a preliminary information setting signal and a preliminary information providing block configured to provide the preliminary information data selected from a plurality of pre-stored preliminary information data to the mode register setting response to the preliminary information setting signal, the selected preliminary information data corresponding to a detected operation parameter detected in response to the preliminary information setting signal.

Abstract: A semiconductor apparatus includes: a slave chip including a signal transfer unit configured to determine whether or not to transfer an input signal in response to a chip select signal; a master chip including a replica circuit unit having the same configuration as the signal transfer unit and a signal output unit configured to receive an output signal of the signal transfer unit and an output signal of the replica circuit unit and generate an output signal in response to the control signal; a first through-chip via vertically formed through the slave chip, and having one end connected to the master chip to receive the input signal and the other end connected to the signal transfer unit; and a second through-chip via vertically formed through the slave chip, and having one end connected to the signal transfer unit and the other end connected to the signal output unit.

Abstract: A data transmission circuit may include a first driving block configured to drive an output terminal for a first time in response to a data driving signal and a level of the output terminal, and a second driving block configured to drive the output terminal for a second time after the first time, in response to the data driving signal.

Abstract: A semiconductor apparatus may include a first semiconductor chip; and a second semiconductor chip configured to transmit/receive signals to/from the first semiconductor chip. Further, a serializer/deserializer (SERDES) configured to serialize/deserialize input/output signals and a data bit inversion (DBI) logic electrically coupled to the SERDES and configured to perform a data inversion function on input/output data of the SERDES may be arranged in a preset region of any one of the first and second semiconductor chips.

Abstract: An integrated circuit system comprising a first chip including a first period signal generation unit configured to generate a first period signal, transmit a first signal applied from a circuit outside of the integrated circuit system to a second chip, and transmit a second signal transmitted from the second chip to the circuit outside of the integrated circuit system, and the second chip including a second period signal generation unit configured to generate a second period signal, a code generation unit configured to generate codes corresponding to a difference between periods of the first period signal and the second period signal, and a delay unit configured to delay the second signal by using a delay value that is changed according to the codes.

Abstract: An integrated circuit chip includes a test circuit suitable for performing a test operation and generating a test result signal indicating whether there is an error or not in the integrated circuit chip, a transmitting unit suitable for transmitting the test result signal through an interlayer channel. The interlayer channel is precharged to a first level before the transmitting unit transmits the test result signal, and the interlayer channel is driven to a second level when there is an error.

Abstract: A flip-flop circuit may include: a latch unit configured to latch an input signal in response to a clock signal; and a timing control unit configured to delay a signal provided from the latch unit by a predetermined time regardless of the clock signal.

Abstract: A semiconductor device includes a plurality of memory chips and a plurality of signal selection units respectively corresponding to the plurality of memory chips, and suitable for commonly transferring test data signals from an external to a corresponding one of the plurality of memory chips during a common test mode, wherein one or more of the plurality of signal selection units may transfer the test data signals from the external to corresponding ones of the plurality of memory chips during an individual test mode, and wherein the semiconductor device may be set to the common test mode when a common test signal is enabled, and set to the individual test mode when both the common test signal and a test control signal are enabled.

Abstract: A power-up circuit of a semiconductor apparatus using a plurality of external power voltages is configured to determine a stableness of the plurality of external power voltages through relative comparison of the plurality of external power voltages, and to activate a power-up signal.

Abstract: A semiconductor apparatus includes a control signal reception portion. The control signal reception portion may set information related to operation of a memory chip by receiving a command signal and an address signal from one among a stack chip test portion, a control signal interface portion and a test setting portion.

Abstract: A semiconductor apparatus includes: a slave chip including a signal transfer unit configured to determine whether or not to transfer an input signal in response to a chip select signal; a master chip including a replica circuit unit having the same configuration as the signal transfer unit and a signal output unit configured to receive an output signal of the signal transfer unit and an output signal of the to replica circuit unit and generate an output signal in response to the control signal; a first through-chip via vertically formed through the slave chip, and having one end connected to the master chip to receive the input signal and the other end connected to the signal transfer unit; and a second through-chip via vertically formed is through the slave chip, and having one end connected to the signal transfer unit and the other end connected to the signal output unit.

Abstract: A semiconductor integrated circuit includes a plurality of semiconductor chips. Each of the plurality of semiconductor chips includes a chip selection unit suitable for generating an internal chip selection signal in response to one or more selective chip selection signals and transferring the selective chip selection signals to an adjacent semiconductor chip of the plurality of semiconductor chips, a selective setting unit suitable for generating a selective internal signal, selectively activated in each semiconductor chip, in response to the internal chip selection signal and an external setting signal, and a common setting unit suitable for generating a common internal signal, activated in common in the plurality of semiconductor chips, in response to the setting signal and an external common chip selection signal.

Abstract: A semiconductor apparatus is provided. The apparatus includes a transmission control unit configured to generate, in response to a received pulse signal having a first pulse width, transmission control signals with a second pulse width larger than the first pulse width and synchronization control signals with a third pulse width larger than the second pulse width. The apparatus also includes a reception control unit configured to generate reception control signals in response to the synchronization control signals.

Abstract: A semiconductor apparatus includes: a slave chip including a signal transfer unit configured to determine whether or not to transfer an input signal in response to a chip select signal; a master chip including a replica circuit unit having the same configuration as the signal transfer unit and a signal output unit configured to receive an output signal of the signal transfer unit and an output signal of the replica circuit unit and generate an output signal in response to the control signal; a first through-chip via vertically formed through the slave chip, and having one end connected to the master chip to receive the input signal and the other end connected to the signal transfer unit; and a second through-chip via vertically formed through the slave chip, and having one end connected to the signal transfer unit and the other end connected to the signal output unit.

Abstract: A semiconductor memory apparatus includes an effective region which is a portion of the memory region and functions as a data storage space, a residual region which is another portion of the memory region, and a capacity control circuit which restricts supply of power and signals to the residual region.

Abstract: A power-up circuit of a semiconductor apparatus using a plurality of external power voltages is configured to determine a stableness of the plurality of external power voltages through relative comparison of the plurality of external power voltages, and to activate a power-up signal.