Patents by Inventor Sang-Joon Hwang
Sang-Joon Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160071561Abstract: A memory device may include a pre-charge control circuit, an active control circuit, and a driver circuit. The pre-charge control circuit may be configured to receive an active command after receiving a pre-charge command for a first bank, determine whether or not a pre-charge operation for the first bank has ended when receiving the active command, and generate an active instruction signal according to a result of the determination. The active control circuit may be configured to generate an active control signal for an active operation according to the active instruction signal. The driver circuit may be configured to control an active operation according to the active control signal.Type: ApplicationFiled: July 16, 2015Publication date: March 10, 2016Inventors: Tae-Yoon LEE, Myeong-O KIM, Kyo-Min SOHN, Sang-Joon HWANG
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Patent number: 9171605Abstract: Provided is a method of detecting a concentrated address of a semiconductor device using an n-bit address. The method includes dividing the n-bit address into k groups, wherein each of n and k is an integer equal to or greater than 2, for each group of the k groups, detecting one or more concentrated sub addresses corresponding to the group, and generating at least one concentrated address by combining the one or more concentrated sub addresses for the k groups.Type: GrantFiled: December 11, 2013Date of Patent: October 27, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Sik Kim, Won-Il Bae, Myeong-O Kim, Min-Soo Kim, Ho-Seok Seol, Min-Sang Park, Kyo-Min Sohn, Chi-Hwan Lee, Sang-Joon Hwang
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Patent number: 9165673Abstract: A semiconductor memory device includes a memory cell array configured to store data including a verification code; a sensing unit configured to sense the stored data including the verification code; and a verification unit configured to determine whether the sensing unit is able to sense the stored data based on a sensing condition, wherein the verification unit is configured to determine whether the sensing unit is able to sense the stored data based on the sensing condition and a value of the verification code sensed by the sensing unit.Type: GrantFiled: March 12, 2013Date of Patent: October 20, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Je-Min Yu, Ho-Young Song, Sung-Min Seo, Sang-Joon Hwang
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Publication number: 20150243374Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.Type: ApplicationFiled: April 28, 2015Publication date: August 27, 2015Inventors: Kyo-Min Sohn, Ho-Young Song, Sang-Joon Hwang, Cheol Kim, Dong-Hyun Sohn
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Publication number: 20150221361Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.Type: ApplicationFiled: October 1, 2014Publication date: August 6, 2015Inventors: Yun-Young Lee, Kyo-Min Sohn, Sang-Joon Hwang, Sung-Min Seo, Sang-Bo Lee, Nak-Won Heo
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Patent number: 9087613Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.Type: GrantFiled: January 29, 2013Date of Patent: July 21, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Kyo-Min Sohn, Ho-Young Song, Sang-Joon Hwang, Cheol Kim, Dong-Hyun Sohn
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Patent number: 8759021Abstract: Provided are a microorganism for use in quantification of homocysteine and methionine and a method of quantifying homocysteine and methionine in a sample by using the microorganism.Type: GrantFiled: May 20, 2010Date of Patent: June 24, 2014Assignee: Labgenomics Co., Ltd.Inventors: Hyun Gyu Park, Min-Ah Woo, Moon Il Kim, Sang-Joon Hwang, Dae-Yeon Cho
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Publication number: 20140143478Abstract: A semiconductor memory device includes a first memory block of a first type of memory; and a second memory block of a second type of memory having a different type from the first type. A first address region of the first memory block and a second address region of the second memory block are included in the same address domain. Each of the first and second memory blocks is accessed by an address signal including an address of the address domain, and the second memory block is a nonvolatile memory.Type: ApplicationFiled: August 30, 2013Publication date: May 22, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Hyun-Sung SHIN, Sang-Joon HWANG, Seung-Man SHIN, In-Su CHOI, Jung-Ho JUNG
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Publication number: 20130242635Abstract: A semiconductor memory device includes a memory cell array configured to store data including a verification code; a sensing unit configured to sense the stored data including the verification code; and a verification unit configured to determine whether the sensing unit is able to sense the stored data based on a sensing condition, wherein the verification unit is configured to determine whether the sensing unit is able to sense the stored data based on the sensing condition and a value of the verification code sensed by the sensing unit.Type: ApplicationFiled: March 12, 2013Publication date: September 19, 2013Applicant: Samsung Electronics Co., Ltd.Inventors: Je-Min YU, Ho-Young SONG, Sung-Min SEO, Sang-Joon HWANG
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Publication number: 20130227344Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.Type: ApplicationFiled: January 29, 2013Publication date: August 29, 2013Inventors: Kyo-Min Sohn, Ho-Young Song, Sang-Joon Hwang, Cheol Kim, Dong-Hyun Sohn
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Publication number: 20130095497Abstract: Provided are a microorganism for use in quantification of homocysteine and methionine and a method of quantifying homocysteine and methionine in a sample by using the microorganism.Type: ApplicationFiled: May 20, 2010Publication date: April 18, 2013Applicant: LABGENOMICS CO., LTD.Inventors: Hyun Gyu Park, Min-Ah Woo, Moon Il Kim, Sang-Joon Hwang, Dae-Yeon Cho
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Patent number: 8379476Abstract: A semiconductor memory device for reducing ripple noise of a back-bias voltage, and a method of driving the semiconductor memory device include a word line driving circuit and a delay logic circuit. The word line driving circuit enables a sub-word line connected to a selected memory cell to a first voltage, and disables the sub-word line of a non-selected memory cell to a second voltage and a third voltage, in response to a sub-word line enable signal, a first word line driving signal, and a second word line driving signal. The delay logic circuit controls the semiconductor memory device so that an amount of charge of the sub-word line that is introduced to the third voltage is greater than an amount of charge of the sub-word line that is introduced to the second voltage by changing a transition point of time of the sub-word line enable signal with respect to a transition point of time of the first word line driving signal, during the disabling of the sub-word line.Type: GrantFiled: January 4, 2011Date of Patent: February 19, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Beom-seop Lee, Young-hyun Jun, Sang-joon Hwang
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Patent number: 8339883Abstract: A semiconductor memory device includes a bitline sensing amp detecting and amplifying data of a pair of bitlines from a memory cell, a column selecting unit transmitting the data of the pair of bitlines to a pair of local datalines in response to a column selecting signal, a dataline precharging unit precharging the pair of local datalines to a precharging voltage level in response to a precharging signal, and a dataline sensing amp detecting and amplifying data transmitted to the pair of local datalines. The dataline sensing amp includes a charge sync unit discharging the pair of local datalines at the precharging voltage level in response to a first dataline sensing enabling signal and data of the pair of local datalines, and a data sensing unit transmitting data of the pair of local datalines to a pair of global datalines in response to a second dataline sensing enabling signal.Type: GrantFiled: November 17, 2010Date of Patent: December 25, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Je-min Yu, Byung-chul Kim, Jun-hyung Kim, Sang-joon Hwang
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Patent number: 8194484Abstract: A bit line pre-charge circuit for a dynamic random access memory (DRAM) uses a charge sharing scheme. The pre-charge circuit includes switching elements disposed between a power voltage node and an output node, capacitors connected between intermediate nodes and ground. The switching elements being operated by successively activated control signals to effectively charge a bit line pair to one half a power voltage using charge sharing between the capacitors.Type: GrantFiled: May 26, 2010Date of Patent: June 5, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Cheon An Lee, Seong Jin Jang, Jong Pil Son, Sang Joon Hwang
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Publication number: 20110176375Abstract: A semiconductor memory device for reducing ripple noise of a back-bias voltage, and a method of driving the semiconductor memory device include a word line driving circuit and a delay logic circuit. The word line driving circuit enables a sub-word line connected to a selected memory cell to a first voltage, and disables the sub-word line of a non-selected memory cell to a second voltage and a third voltage, in response to a sub-word line enable signal, a first word line driving signal, and a second word line driving signal. The delay logic circuit controls the semiconductor memory device so that an amount of charge of the sub-word line that is introduced to the third voltage is greater than an amount of charge of the sub-word line that is introduced to the second voltage by changing a transition point of time of the sub-word line enable signal with respect to a transition point of time of the first word line driving signal, during the disabling of the sub-word line.Type: ApplicationFiled: January 4, 2011Publication date: July 21, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Beom-seop Lee, Young-hyun Jun, Sang-joon Hwang
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Publication number: 20110116334Abstract: A semiconductor memory device includes a bitline sensing amp detecting and amplifying data of a pair of bitlines from a memory cell, a column selecting unit transmitting the data of the pair of bitlines to a pair of local datalines in response to a column selecting signal, a dataline precharging unit precharging the pair of local datalines to a precharging voltage level in response to a precharging signal, and a dataline sensing amp detecting and amplifying data transmitted to the pair of local datalines. The dataline sensing amp includes a charge sync unit discharging the pair of local datalines at the precharging voltage level in response to a first dataline sensing enabling signal and data of the pair of local datalines, and a data sensing unit transmitting data of the pair of local datalines to a pair of global datalines in response to a second dataline sensing enabling signal.Type: ApplicationFiled: November 17, 2010Publication date: May 19, 2011Inventors: Je-min YU, Byung-chul Kim, Jun-hyung Kim, Sang-joon Hwang
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Publication number: 20110002183Abstract: A bit line pre-charge circuit for a dynamic random access memory (DRAM) uses a charge sharing scheme. The pre-charge circuit includes switching elements disposed between a power voltage node and an output node, capacitors connected between intermediate nodes and ground. The switching elements being operated by successively activated control signals to effectively charge a bit line pair to one half a power voltage using charge sharing between the capacitors.Type: ApplicationFiled: May 26, 2010Publication date: January 6, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Cheon An LEE, Seong Jin JANG, Jong Pil SON, Sang Joon HWANG
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Patent number: 7440340Abstract: A data output buffer includes an output terminal, a buffer and a pull-down driver. The output terminal is coupled to a first end of a transmission line, the transmission line being coupled to a pull-up termination resistor at a second end. The buffer pulls up the output terminal to a first power supply voltage and pulls down the output terminal to a second power supply voltage based on an output data signal. The pull-down driver pre-emphasizes an initial stage of a pull-down driving operation of the output terminal based on the output data.Type: GrantFiled: October 18, 2005Date of Patent: October 21, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Joon Hwang, Dong-Jin Lee, Jung-Bae Lee
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Publication number: 20080231350Abstract: An internal voltage generating circuit for use in a semiconductor memory device includes a reference voltage input terminal to receive a reference voltage, a comparison unit to output a first internal voltage, the first internal voltage having a voltage level based at least in part on the reference voltage, a first feedback unit to receive the first internal voltage and an external voltage and to provide a first feedback internal voltage to the comparison unit, a loading circuit to output a second internal voltage, and a second feedback unit to receive the second internal voltage from the loading circuit and to provide a second feedback internal voltage to the comparison unit.Type: ApplicationFiled: March 19, 2008Publication date: September 25, 2008Inventor: Sang-Joon Hwang
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Patent number: 7205799Abstract: We describe an input buffer having a stabilized operating point and an associated method. An input buffer may include a first differential amplifying unit to generate a first output signal having a first operating point and a second differential amplifying unit to generate a second output signal having a second operating point. An output control circuit varies respective weights of the first and second output signals responsive to an output control signal. The first differential amplifying unit may operate responsive to a reference voltage and an input voltage signal. The second differential amplifying unit may operate responsive to the reference voltage and the input voltage signal. The first operating point may be relatively higher than the second operating point.Type: GrantFiled: September 13, 2005Date of Patent: April 17, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Jin Kim, Seong-Jin Jang, Kwang-II Park, Sang-Joon Hwang, Ho-Young Song, Ho-Kyong Lee, Woo-Jin Lee