Abstract: The present disclosure relates to an electrolyte solution for a lithium secondary battery capable of improving the output and lifespan characteristics at high temperature of a lithium secondary battery, and a lithium secondary battery including the same. An electrolyte solution for a lithium secondary battery includes a lithium salt, a solvent, and a functional additive, wherein the functional additive includes a positive-electrode film additive, which is 3-(4-cyano-5-(4-nitrophenyl)-1H-1,2,3-triazol-1-yl)propyl methanesulfonate.

Abstract: The present disclosure relates to an electrolyte solution for a lithium secondary battery capable of improving the output and lifespan characteristics at high temperature of a lithium secondary battery, and a lithium secondary battery including the same. An electrolyte solution for a lithium secondary battery includes a lithium salt, a solvent, and a functional additive, wherein the functional additive includes a first electrode film additive, which is 3-(4-cyano-5-(4-nitrophenyl)-1H-1,2,3-triazol-1-yl)propyl 4-methylbenzenesulfonate.

Abstract: A power source switching circuit for a memory device includes: a first power source voltage terminal for supplying a first power source voltage, a second power source voltage terminal for supplying a second power source voltage, a first metal-oxide-semiconductor field-effect transistor (MOSFET) and a second MOSFET connected in series with the first power source voltage terminal, a first level shifter connected to the first MOSFET and supplied with the first power source voltage, a second level shifter connected to the second MOSFET and supplied with the second power source voltage, a third MOSFET connected to the second MOSFET, and a third level shifter connected to the third MOSFET and supplied with a third power source voltage, and a memory cell of a non-volatile memory is programmed using the first power source voltage or the second power source voltage.

Abstract: A scan driver includes: a first transistor having a first electrode coupled to an output scan line, a second electrode coupled to a first power line, and a gate electrode coupled to a first node; a second transistor having a first electrode coupled to a first clock line, a second electrode coupled to the output scan line, and a gate electrode coupled to a second node; a third transistor having a first electrode coupled to the first node, a second electrode coupled to a first input scan line, and a gate electrode coupled to a second clock line; and a fourth transistor having a first electrode coupled to the second node and a second electrode and a gate electrode, which are coupled to a second input scan line, wherein the first input scan line and the second input scan line are different from each other.

Abstract: An inter-floor transport system includes a first interface unit at a first floor and configured to receive containers from a transport vehicle, and a car configured to receive containers from the first interface unit at the first floor and move containers to a second floor, where the car includes a cage, a storage unit in the cage and including a plurality of storage areas, and an arrangement unit in the cage, the arrangement unit being configured to receive containers from the first interface unit and store containers in respective storage areas of the plurality of storage areas of the storage unit.

Abstract: A portable air flow apparatus may include a base configured to be seated on a surface, a head comprising a suction inlet through which air is suctioned into the head and a discharge outlet through which the air suctioned in through the suction inlet is discharged, the suction inlet and the discharge outlet being horizontally spaced apart from each other at a right angle with respect to a vertical direction, and a column that connects the head and the base in such a manner that the head is vertically spaced from the base.

Abstract: A battery module ac includes a cell stack in which a plurality of battery cells are vertically stacked; a module housing including a base plate supporting the cell stack, and a pair of side plates covering both side portions of the cell stack and each including a spark direction changing portion formed by bending an end portion of the side plate in a longitudinal direction of the side plate toward the cell stack; and a bus bar frame assembly covering an opening portion formed on a side of the module housing in a longitudinal direction of the module housing, the bus bar frame assembly including a bus bar frame coupled to a side of the cells tack in a longitudinal direction of the cell stack and a bus bar located on the bus bar frame and coupled to an electrode lead of the battery cell.

Abstract: A battery module includes a cell stack in which a plurality of battery cells are vertically stacked; a module housing including a base plate supporting the cell stack and a pair of side plates covering both side portions of the cell stack; a bus bar frame assembly covering an opening portion formed on a side of the module housing in a longitudinal direction of the module housing; and a plurality of spark delay portions protruding from an inner surface of each of the pair of side plates and spaced apart from one another in a height direction of the side plate.

Abstract: A battery pack includes a sub-pack including a plurality of battery modules that are located adjacent to one another; a duct coupled to a side of the sub-pack in a width direction of the sub-pack; and a duct cover covering a duct opening portion formed on a side of the duct in a longitudinal direction of the duct, the duct cover including a filter having a mesh structure.

Abstract: A system on chip includes first to third nanowires extending in a second direction, first to third gate lines respectively surrounding the first to third nanowires, each of the first to third gate lines extending in a first direction across the second direction, a gate isolation region cutting the first to third gate lines and extending in the second direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact; and a second metal line electrically connected to the first gate contact.

Abstract: A system on chip includes first to third nanowires extending in a second direction, first to third gate lines respectively surrounding the first to third nanowires, each of the first to third gate lines extending in a first direction across the second direction, a gate isolation region cutting the first to third gate lines and extending in the second direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact; and a second metal line electrically connected to the first gate contact.

Abstract: A method is provided. The method includes forming a first to third gate lines on a substrate, the second gate line formed between the first and third gate lines; forming a gate isolation region to cut the first to third gate lines into two first sub gate lines, two second sub gate lines and two third sub gate lines, respectively; forming a first gate contact on one of the two first sub gate lines; forming a second gate contact on the two second sub gate lines; forming a third gate contact on one of the two third sub gate lines; forming a first metal line to connect the first and third gate contacts; and forming a second metal line. The first to third gate lines extend in a first direction, and the gate isolation region extends in a second direction different from the first direction.

Abstract: A method is provided. The method includes forming a first to third gate lines on a substrate, the second gate line formed between the first and third gate lines; forming a gate isolation region to cut the first to third gate lines into two first sub gate lines, two second sub gate lines and two third sub gate lines, respectively; forming a first gate contact on one of the two first sub gate lines; forming a second gate contact on the two second sub gate lines; forming a third gate contact on one of the two third sub gate lines; forming a first metal line to connect the first and third gate contacts; and forming a second metal line. The first to third gate lines extend in a first direction, and the gate isolation region extends in a second direction different from the first direction.

Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.

Abstract: Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.

Abstract: A method of manufacturing a semiconductor device includes forming transistors in a cell region of a test wafer, forming a first test pattern on a first test cell in the cell region, the first test pattern being electrically connected to the transistors, and scanning the first test pattern using an electron beam. Forming the transistors in the cell region includes patterning an upper portion of the test wafer to form active patterns, forming source/drain regions on the active patterns, forming gate electrodes extending across the active patterns, forming active contacts coupled to the source/drain regions, and forming gate contacts coupled to the gate electrodes.

Abstract: A method of manufacturing an integrated circuit, a system for carrying out the method, and a system for verifying an integrated circuit may use a standard cell layout including a first layout region that may violate design rules. The method for designing an integrated circuit may comprise receiving a data file that includes a scaling enhanced circuit layout, and designing a first standard cell layout using design rules and the data file. The designing the first standard cell layout may include designing a first layout region of the first standard cell layout using the data file, and designing a second region of the first standard cell layout using the design rules.

Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.

Abstract: A method of designing a semiconductor integrated circuit (IC) is provided as follows. A standard cell library is generated. The standard cell library includes characteristic information for a plurality of standard cells. The characteristic information includes a characteristic of each standard cell. A characteristic change region is detected. The characteristic change region includes at least one of the plurality of standard cells by comparing characteristics of standard cells to be placed adjacent to the characteristic change region, based on the standard cell library. A characteristic of the at least one standard cell included in the detected characteristic change region is changed to one of the characteristics of the standard cells to be placed adjacent to the characteristic change region to update the standard cell library. A plurality of standard cells of the updated standard cell library is placed.

Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.