Patents by Inventor Sang-Kyun Han
Sang-Kyun Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11981659Abstract: The present invention relates to novel mesylate salt of N-(5-(4-(4-((dimethylamino)methyl)-3-phenyl-1H-pyrazol-1-yl)pyrimidine-2-ylamino)-4-methoxy-2-morpholinophenyl)acrylamide, a novel crystalline form thereof, and a process for preparing the same. More specifically, the present invention relates to mesylate salt of N-(5-(4-(4-((dimethylamino)methyl)-3-phenyl-1H-pyrazol-1-yl)pyrimidine-2-ylamino)-4-methoxy-2-morpholinophenyl)acrylamide, which is excellent in stability, solubility, and bioavailability when it is administered not only alone but also in combination with other drugs and which has a high purity, a crystalline form thereof, and a process for preparing the same.Type: GrantFiled: March 17, 2022Date of Patent: May 14, 2024Assignee: Yuhan CorporationInventors: Sang Ho Oh, Jong Gyun Kim, Se-Woong Oh, Tae Dong Han, Soo Yong Chung, Seong Ran Lee, Kyeong Bae Kim, Young Sung Lee, Woo Seob Shin, Hyun Ju, Jeong Ki Kang, Su Min Park, Dong Kyun Kim
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Publication number: 20240084126Abstract: A graft copolymer, and a graft copolymer composition having excellent particulate dispersibility in a curable resin such as an epoxy resin and is applicable as a particulate impact reinforcing agent, a curable resin composition including same, and methods of preparing them.Type: ApplicationFiled: August 12, 2022Publication date: March 14, 2024Applicant: LG Chem, Ltd.Inventors: Min Ah Jeong, Ki Hyun Yoo, Sang Hoon Han, Yong Kyun Kim
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Patent number: 9516227Abstract: Various embodiments provide a camera that includes a non-touch switch that can be utilized to access and activate various camera functionality.Type: GrantFiled: January 7, 2016Date of Patent: December 6, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Seang Y. Chau, Amy Aimei Han, Michael J. Lammers, Sang-Kyun Han
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Publication number: 20160119544Abstract: Various embodiments provide a camera that includes a non-touch switch that can be utilized to access and activate various camera functionality.Type: ApplicationFiled: January 7, 2016Publication date: April 28, 2016Inventors: Seang Y. Chau, Amy Aimei Han, Michael J. Lammers, Sang-Kyun Han
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Patent number: 9282244Abstract: Various embodiments provide a wearable camera that can be worn by a user. In one or more embodiments, the wearable camera can include a non-touch switch that can be utilized to access and activate various camera functionality.Type: GrantFiled: April 29, 2013Date of Patent: March 8, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Seang Y. Chau, Amy Aimei Han, Michael J. Lammers, Sang-Kyun Han
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Publication number: 20140270688Abstract: In one or more embodiments, a camera includes a replay mode which, when selected, the camera automatically captures image data, such as video or still images, and saves the image data to a memory buffer. The size of the memory buffer may be set by the user to determine how much image data is to be collected. If an event occurs that the user wishes to memorialize through video or still images, a record button can be activated which saves the image data from the beginning of the memory buffer and continues recording until the user presses the record button again.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: Microsoft CorporationInventors: Amy Aimei Han, Michael J. Lammers, Sang-Kyun Han, Seang Y. Chau
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Publication number: 20140270689Abstract: Various embodiments provide a wearable camera that can be worn by a user. In one or more embodiments, the wearable camera can include a non-touch switch that can be utilized to access and activate various camera functionality.Type: ApplicationFiled: April 29, 2013Publication date: September 18, 2014Applicant: Microsoft CorporationInventors: Seang Y. Chau, Amy Aimei Han, Michael J. Lammers, Sang-Kyun Han
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Publication number: 20120201085Abstract: Circuits and methods for suppressing integrated circuit leakage currents are described. Many of these circuits and methods are particularly well-suited for use in dynamic memory circuits. Examples describe the use of power, ground, or both and power and ground source transistors used for generating virtual voltages. An aspect of the invention describes lowering refresh current. An aspect describes reducing the standby current. An aspect of the invention describes lowering leakage resulting from duplicated circuits, such as row decoders and word line drivers. An aspect describes methods of performing early wake-up of source transistors. A number of source transistor control mechanisms are taught. Circuit layouts methods are taught for optimizing integrated circuit layouts using the source transistors.Type: ApplicationFiled: April 19, 2011Publication date: August 9, 2012Applicant: ZMOS TECHNOLOGY, INC.Inventors: Seung-Moon Yoo, Myung Chan Choi, Young Tae Kim, Jung Ju Son, Sang-Kyun Han, Sun Hyoung Lee
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Patent number: 7929367Abstract: Circuits and methods for suppressing integrated circuit leakage currents are described. Many of these circuits and methods are particularly well-suited for use in dynamic memory circuits. Examples describe the use of power, ground, or both and power and ground source transistors used for generating virtual voltages. An aspect of the invention describes lowering refresh current. An aspect describes reducing the standby current. An aspect of the invention describes lowering leakage resulting from duplicated circuits, such as row decoders and word line drivers. An aspect describes methods of performing early wake-up of source transistors. A number of source transistor control mechanisms are taught. Circuit layouts methods are taught for optimizing integrated circuit layouts using the source transistors.Type: GrantFiled: September 22, 2006Date of Patent: April 19, 2011Assignee: Zmos Technology, Inc.Inventors: Seung-Moon Yoo, Myung Chan Choi, Young Tae Kim, Sung Ju Son, Sang-Kyun Han, Sun Hyoung Lee
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Patent number: 7705625Abstract: Source transistor configurations are described for reducing leakage and delay within integrated circuits. Virtual power and ground nodes are supported with the use of stacked transistor configurations, such as a two transistor stack between a first virtual supply connection and VSS, and a second virtual supply connection and VDD. Gate drives of these stacked transistors are modulated with different voltage levels in response to the operating power mode of the circuit, for example active mode, active-standby mode, and deep power-down mode. Means for driving these source stacks are described. In one embodiment separate virtual nodes are adapted for different types of circuits, such as buffers, row address strobe, and column address strobe. Other techniques, such as directional placement of the transistors is also described.Type: GrantFiled: July 6, 2006Date of Patent: April 27, 2010Assignee: Zmos Technology, Inc.Inventors: Seung-Moon Yoo, Jae Hoon Yoo, Jeongduk Sohn, Sung Ju Son, Myung Chan Choi, Young Tae Kim, Oh Sang Yoon, Sang-Kyun Han
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Patent number: 7522464Abstract: Dynamic Random Access Memory (DRAM) circuits and methods are described for reducing leakage and increasing repaired yield. These objects are accomplished according to the invention by grouping refresh cycles within a single activation of power control, the use of limiting circuits or fuses to mitigate power losses associated with micro-bridging of bit-lines and word-lines, modulating the bit-line voltage at the end of precharge cycles, configuring refresh control circuits to use redundant word-lines in generating additional refresh cycles for redundant rows of memory cells, and combinations thereof. In one aspect, word-line fuses indicate modes of use as: unused, replacement, additional refresh, and replacement with additional refresh. The refresh control circuit utilizes these modes in combination with the X-address stored in the word-line fuses for controlling the generation of additional refresh cycles toward overcoming insufficient data retention intervals in select memory cell rows.Type: GrantFiled: July 18, 2007Date of Patent: April 21, 2009Assignee: ZMOS Technology, Inc.Inventors: Seung-Moon Yoo, Myung Chan Choi, Sangho Shin, Sang-Kyun Han
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Publication number: 20080031068Abstract: Dynamic Random Access Memory (DRAM) circuits and methods are described for reducing leakage and increasing repaired yield. These objects are accomplished according to the invention by grouping refresh cycles within a single activation of power control, the use of limiting circuits or fuses to mitigate power losses associated with micro-bridging of bit-lines and word-lines, modulating the bit-line voltage at the end of precharge cycles, configuring refresh control circuits to use redundant word-lines in generating additional refresh cycles for redundant rows of memory cells, and combinations thereof. In one aspect, word-line fuses indicate modes of use as: unused, replacement, additional refresh, and replacement with additional refresh. The refresh control circuit utilizes these modes in combination with the X-address stored in the word-line fuses for controlling the generation of additional refresh cycles toward overcoming insufficient data retention intervals in select memory cell rows.Type: ApplicationFiled: July 18, 2007Publication date: February 7, 2008Applicant: ZMOS TECHNOLOGY, INC.Inventors: Seung-Moon Yoo, Myung Choi, Sangho Shin, Sang-Kyun Han
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Publication number: 20070081405Abstract: Circuits and methods for suppressing integrated circuit leakage currents are described. Many of these circuits and methods are particularly well-suited for use in dynamic memory circuits. Examples describe the use of power, ground, or both and power and ground source transistors used for generating virtual voltages. An aspect of the invention describes lowering refresh current. An aspect describes reducing the standby current. An aspect of the invention describes lowering leakage resulting from duplicated circuits, such as row decoders and word line drivers. An aspect describes methods of performing early wake-up of source transistors. A number of source transistor control mechanisms are taught. Circuit layouts methods are taught for optimizing integrated circuit layouts using the source transistors.Type: ApplicationFiled: September 22, 2006Publication date: April 12, 2007Applicant: ZMOS TECHNOLOGY, INC.Inventors: Seung-Moon Yoo, Myung Chan Choi, Young Tae Kim, Sung Ju Son, Sang-Kyun Han, Sun Hyoung Lee
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Publication number: 20070063763Abstract: Source transistor configurations are described for reducing leakage and delay within integrated circuits. Virtual power and ground nodes are supported with the use of stacked transistor configurations, such as a two transistor stack between a first virtual supply connection and VSS, and a second virtual supply connection and VDD. Gate drives of these stacked transistors are modulated with different voltage levels in response to the operating power mode of the circuit, for example active mode, active-standby mode, and deep power-down mode. Means for driving these source stacks are described. In one embodiment separate virtual nodes are adapted for different types of circuits, such as buffers, row address strobe, and column address strobe. Other techniques, such as directional placement of the transistors is also described.Type: ApplicationFiled: July 6, 2006Publication date: March 22, 2007Inventors: Seung-Moon Yoo, Jae Yoo, Jeongduk Sohn, Sung Son, Myung Choi, Young Kim, Oh Yoon, Sang-Kyun Han