Abstract: A mobile device and an operation method thereof are provided. The method includes removing a Subscriber Identity Module (SIM) card, previously inserted into the mobile device, from the mobile device, determining whether a SIM card, identical to or different from the removed SIM card, is inserted into the mobile device, and, managing base station-related information, wherein the managing of the base station-related information comprises at least one of updating the base station-related information with base station-related information newly acquired by performing a base station-related protocol procedure based on a newly inserted SIM card, according to at least one of the type and the insertion time point of the newly inserted SIM card, and maintaining base station-related information stored based on the removed SIM card. According to the embodiments of the invention, an additional bootstrapping process is not required when the mobile device user removes or inserts a SIM card from or into the mobile device.

Abstract: A protocol processing method and apparatus are disclosed for a multi-SIM terminal holding multiple subscriber identification cards. The method includes: determining whether all the subscriber identification cards are associated with the same base station (e.g., a Public Land Mobile Network); and conducting, when all the subscriber identification cards are associated with the same base station, frequency scanning and measurement for a selected one of the subscriber identification cards, and sharing the results of frequency scanning and measurement with all the subscriber identification cards. Hence, the multi-SIM terminal may reduce battery power consumption without repeated frequency scanning and measurement for multiple subscriber identification cards.

Abstract: A ferroelectric capacitor having a three-dimensional structure, a nonvolatile memory device having the same, and a method of fabricating the same are provided. The ferroelectric capacitor may include a trench-type lower electrode, at least one layer formed around the lower electrode, a ferroelectric layer (PZT layer) formed on the lower electrode and the at least one layer and an upper electrode formed on the ferroelectric layer. The at least one layer may be at least one insulating interlayer and the at least one layer may also be at least one diffusion barrier layer. The at least one layer may be formed of an insulating material excluding SiO2 or may have a perovskite crystal structure excluding Pb.

Abstract: Provided is a nonvolatile semiconductor memory device and a method of manufacturing the same. The nonvolatile semiconductor memory device may include a tunnel insulating layer formed on a semiconductor substrate, a charge trap layer including a dielectric layer doped with a transition metal formed on the tunnel insulating layer, a blocking insulating layer formed on the charge trap layer, and a gate electrode formed on the blocking insulating layer. The dielectric layer may be a high-k dielectric layer, for example, a HfO2 layer. Thus, the data retention characteristics of the nonvolatile semiconductor memory device may be improved because a deeper charge trap may be formed by doping the high-k dielectric layer with a transition metal.

Abstract: Provided are a charge trap semiconductor memory device including a charge trap layer on a semiconductor substrate, and a method of manufacturing the charge trap semiconductor memory device. The method includes: (a) coating a first precursor material on a surface of a semiconductor substrate to be deposited and oxidizing the first precursor material to form a first layer formed of an insulating material; (b) coating a second precursor material formed of metallicity on the first layer; (c) supplying the first precursor material on the surface coated with the second precursor material to substitute the second precursor material with the first precursor material; and (d) oxidizing the first and second precursor materials obtained in (c) to form a second layer formed of an insulating material and a metal impurity, and (a) through (d) are performed at least one time to form a charge trap layer having a structure in which the metal impurity is isolated in the insulating material.

Abstract: A ferroelectric capacitor comprises a first electrode comprising an alloy of Ir and Ru, a ferroelectric layer disposed on the first electrode, and a second electrode disposed on the ferroelectric layer. A ferroelectric memory comprises a substrate and a plurality of memory cells arranged on the substrate. Each memory cell comprises a first electrode comprising an alloy of Ir and Ru, a ferroelectric layer disposed on the first electrode, and a second electrode disposed on the ferroelectric layer.

Abstract: A semiconductor memory device may include a semiconductor substrate, at least one control gate electrode, at least one storage node layer, at least one tunneling insulating layer, at least one blocking insulating layer, and/or first and second channel regions. The at least one control gate electrode may be recessed into the semiconductor substrate. The at least one storage node layer may be between a sidewall of the at least one control gate electrode and the semiconductor substrate. The at least one tunneling insulating layer may be between the at least one storage node layer and the at least one control gate electrode. The at least one blocking insulating layer may be between the storage node layer and the control gate electrode. The first and second channel regions may be between the at least one tunneling insulating layer and the semiconductor substrate to surround at least a portion of the sidewall of the control gate electrode and/or may be separated from each other.

Abstract: A semiconductor memory device may include a semiconductor substrate, a control gate electrode recessed in the semiconductor substrate, a storage node layer between the control gate electrode and the semiconductor substrate, a tunneling insulating layer between the storage node layer and the semiconductor substrate, a blocking insulating layer between the storage node layer and the control gate electrode, and first and second channel regions surrounding the control gate electrode and separated by a pair of opposing separating insulating layers. A method of operating the semiconductor memory device may include programming data in the storage node layer by charge tunneling through the blocking insulating layer, thus achieving relatively high reliability and efficiency.

Abstract: A semiconductor memory device with a dual storage node structure as well as methods of fabricating and operating such a device are provided. The semiconductor memory device includes a substrate, a first transistor formed on the substrate, a first storage node connected to a source region of the first transistor, a second storage node connected to a drain region of the first transistor, and a plate line commonly contacting the first storage node and the second storage node.

Abstract: A ferroelectric capacitor comprises a first electrode comprising an alloy containing a first element and a second element of the periodic table of the elements, the first element being selected from the group consisting of Ir and Ru. A ferroelectric layer is disposed on the first electrode, wherein the ferroelectric layer comprises a ferroelectric material containing the second element. A second electrode is disposed on the ferroelectric layer. The ferroelectric capacitor can be provided as part of a memory cell of a ferroelectric memory.

Abstract: A memory device and method for operating the same are provided. The example method may be directed to a method of performing a memory operation on a memory device, and may include applying a negative voltage bias to the memory device during a programming operation of the memory device and applying a positive voltage bias to the memory device during an erasing operation of the memory device. The example memory device may include a substrate and a gate structure formed on the substrate, the gate structure exhibiting a faster flat band voltage shift under a negative voltage bias than under a positive voltage bias, the gate structure receiving a negative voltage bias during a programming of the memory device and receiving a positive voltage bias during an erasing operation of the memory device.

Abstract: A multi bits flash memory device and a method of operating the same are disclosed.

Abstract: A ferroelectric capacitor comprises a first electrode comprising an alloy of Ir and Ru, a ferroelectric layer disposed on the first electrode, and a second electrode disposed on the ferroelectric layer. A ferroelectric memory comprises a substrate and a plurality of memory cells arranged on the substrate. Each memory cell comprises a first electrode comprising an alloy of Ir and Ru, a ferroelectric layer disposed on the first electrode, and a second electrode disposed on the ferroelectric layer.

Abstract: A ferroelectric capacitor comprises a first electrode comprising an alloy of Ir and Ru, a ferroelectric layer disposed on the first electrode, and a second electrode disposed on the ferroelectric layer. A ferroelectric memory comprises a substrate and a plurality of memory cells arranged on the substrate. Each memory cell comprises a first electrode comprising an alloy of Ir and Ru, a ferroelectric layer disposed on the first electrode, and a second electrode disposed on the ferroelectric layer.

Abstract: A mobile station designed to skip sensitivity measuring of neighboring cells when a specific condition is satisfied and a power management process thereof. The mobile station checks a movement of the mobile station during a reference time T using a motion sensor; and if the movement of the mobile station is not detected during the reference time T, enters an enhanced mode and skipping at least one procedure selected from the group consisting of a procedure of measuring sensitivities of neighboring cells, a procedure of re-selecting a cell and a procedure of tuning with the neighboring cells. This can reduce power consumption in the mobile station, which is fixed for a long time. The power management process can be applied to various types communication systems such as GSM, GPRS, CDMA, WCDMA, HSDPA, HSUPA and TDS-CDMA, in which cell re-selection is carried out.

Abstract: An air knife capable of preventing drying defects during substrate drying processes includes an inlet through which air is supplied from an outside of the air knife, a chamber which stores the air flowing through the inlet, and an outlet which is connected to the chamber and sprays the air stored in the chamber on a substrate, and a main body having a lower end portion extending from the outlet and past at least a portion of the chamber, wherein an angle between the lower end portion of the main body and a body reference line extended from the outlet is less than 40 degrees.

Abstract: Provided is a method for manufacturing a material layer capable of increasing the deposition rate of a noble metal layer on a ferroelectric layer, a method for manufacturing a ferroelectric capacitor using the same, a ferroelectric capacitor manufactured by the same method, and a semiconductor memory device having the ferroelectric capacitor and a manufacturing method thereof. According to a method for manufacturing the material layer, a ferroelectric layer is formed. The ferroelectric layer may be exposed to seed plasma, and a material layer including a source material of the seed plasma may be formed on a region of the ferroelectric layer exposed to the seed plasma.

Abstract: Provided are a charge trap memory device and a method of manufacturing the same. The charge trap memory device may comprise a gate structure including a plurality of metal oxide nanodots discontinuously arranged as a charge trap site on a substrate.

Abstract: Provided are methods of forming nano crystals and method of manufacturing a memory device suing the same. In an example embodiment, a method of forming nano crystals may include forming an amorphous film on a substrate and converting the amorphous film into an oxide film having the nano crystals by annealing the amorphous film under oxidizing conditions under which part of the crystallized film is oxidized.

Abstract: Provided are a charge trap semiconductor memory device including a charge trap layer on a semiconductor substrate, and a method of manufacturing the charge trap semiconductor memory device. The method includes: (a) coating a first precursor material on a surface of a semiconductor substrate to be deposited and oxidizing the first precursor material to form a first layer formed of an insulating material; (b) coating a second precursor material formed of metallicity on the first layer; (c) supplying the first precursor material on the surface coated with the second precursor material to substitute the second precursor material with the first precursor material; and (d) oxidizing the first and second precursor materials obtained in (c) to form a second layer formed of an insulating material and a metal impurity, and (a) through (d) are performed at least one time to form a charge trap layer having a structure in which the metal impurity is isolated in the insulating material.