Abstract: A system for a memory module mounting test according to an embodiment of the present disclosure includes: a test tray on which a memory module array in which a plurality of memory modules are positioned in a predetermined pattern is loaded; a tester in which the test tray is able to be seated and a socket corresponding to the predetermined pattern is formed to perform a test on the memory module array; a transfer for transferring the test tray from an initial position to a seating position where the test tray is seated in the tester; and a mounter for mounting the memory module array transferred to the seating position in the socket.

Abstract: A child anchor for a vehicle can be moved down and hidden in a seat by a user operating the apparatus with the seat changed into a full flat state, whereby it is possible to prevent contact between the child anchor and a passenger who takes a rest in the seat in the full flat state. Accordingly, there is an advantage that it is possible to improve convenience for a passenger who takes a rest.

Abstract: A binder for a lithium-sulfur electrode is proposed. The binder can improve the capacity and lifespan characteristics of a lithium-sulfur secondary battery by suppressing the shuttle reaction due to the elution of polysulfide through the interaction of lithium polysulfide while maintaining the binding characteristics of the binder. This binder may be used for a positive electrode and a lithium-sulfur secondary battery. The binder may include a modified polyvinylidene fluoride (PVdF)-based binder that is soluble in an organic solvent. The modified PVdF-based binder may include a PVdF-based main chain and a functional group having a carboxylic group or carbonyl group grafted as a side chain.

Abstract: The present disclosure discloses a method of generating a master state that is a normal state in a repeated cycle by analyzing log data output from a programmable logic controller (PLC). In addition, a method of generating log data as graph data as data preprocessing for generating a master state is disclosed. The method of generating a master pattern and the method of training a cycle analysis model according to the present disclosure are different from the related art in that the methods are a technology of processing a machine control language (low-level language) that is difficult for humans to analyze and converting the machine control language into an analyzable language (high-level language), i.e., a machine language processing (MLP)-based technology that analyzes the executed machine language (a language that controls a machine) with a computer and can be understood by humans.

Abstract: Integrated circuit devices including a via and methods of forming the same are provided. The methods may include forming a conductive wire structure on a substrate. The conductive wire structure may include a first insulating layer and a conductive wire stack in the first insulating layer, and the conductive wire stack may include a conductive wire and a mask layer stacked on the substrate. The method may also include forming a recess in the first insulating layer by removing the mask layer, the recess exposing the conductive wire, forming an etch stop layer and then a second insulating layer on the first insulating layer and in the recess of the first insulating layer, and forming a conductive via extending through the second insulating layer and the etch stop layer and contacting the conductive wire.

Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.

Abstract: A unit page buffer block includes first to fourth page buffer pairs. Each of the page buffer pairs includes a common column decoder block; and an upper page buffer stage and a lower page buffer stage electrically and commonly connected to the common column decoder block. Each of the upper page buffer stages includes an upper selection block; an upper latch block; and an upper cache block. Each of the lower page buffer stage includes a lower selection block; a lower latch block; and a lower cache block. Each of the upper selection blocks includes first to fourth sub-selection blocks. Each of the upper and lower latch blocks includes first to twelfth upper sub-latch blocks. Each of the upper and lower cache blocks includes first to twelfth upper sub-cache blocks. Each of the common column decoder block includes first to third sub-common column decoder blocks arranged in a row direction.

Abstract: The austenitic stainless steel that does not cause defects such as aging crack or delayed fracture even after the expansion and curling process of 5 steps or more is disclosed. In accordance with an aspect of the present disclosure, an austenitic stainless steel with excellent pipe expanding workability and aging crack resistance includes, in percent (%) by weight of the entire composition, C: 0.01 to 0.04%, Si: 0.1 to 1.0%, Mn: 0.1 to 2.0%, Cr: 16 to 20%, Ni: 6 to 10%, Cu: 0.1 to 2.0%, Mo: 0.2% or less, N: 0.035 to 0.07%, the remainder of iron (Fe) and other inevitable impurities, and the C+N satisfies 0.1% or less, the product of the Md30 (° C.) value and average grain size (?m) satisfies less than ?500.

Abstract: An embodiment includes: a base; a circuit board which is disposed on the base and which includes first and second terminals; a housing disposed on the circuit board; a bobbin disposed in the housing; a first coil disposed on the bobbin; a sensing magnet disposed on the bobbin; a magnet disposed in the housing; a first position sensor which is disposed in the housing and which corresponds to the sensing magnet; a second coil disposed between the base and the magnet; and a second position sensor which is disposed on the circuit board and which includes a first sensor and a second sensor, wherein each of the first sensor and the second sensor is a driver integrated circuit including a hall sensor and a driver, a clock signal is provided to the first terminal of the circuit board, a data signal is provided to the second terminal of the circuit board, and the driver of each of the first position sensor, the first sensor, and the second sensor transmits/receives the clock signal through the first terminal of the ci

Abstract: A stainless steel with a yield strength of 2,200 MPa or more is disclosed through the generation of the strain-induced martensite phase and the increase of the martensite phase strength. A high strength stainless steel according to an embodiment of present disclosure includes, in percent (%) by weight of the entire composition, C: 0.14 to 0.20%, Si: 0.8 to 1.0%, Mn: more than 0 and 0.5% or less, Cr: 15.0 to 17.0%, Ni: 4.0 to 5.0%, Mo: 0.6 to 0.8%, Cu: 0.5% or less, N: 0.05 to 0.11%, the remainder of iron (Fe) and other inevitable impurities, and C+N: 0.25% or more and Md30 value satisfies 40° C. or more.

Abstract: A semiconductor package is provided. The semiconductor package can include a first redistributed layer on which a plurality of semiconductor chips and a plurality of passive devices are mounted on one surface, a second redistributed layer electrically connected to the first redistributed layer through a via, an external connection terminal formed on the lower surface of the second redistributed layer, a first mold provided to cover the plurality of semiconductor chips and the plurality of passive devices on the first redistributed layer, and a second mold provided between the first redistributed layer and the second redistributed layer. Each of the first redistributed layer and the second redistributed layer includes a wiring pattern and an insulating layer and is composed of a plurality of layers, and at least one of the plurality of semiconductor chips is disposed between the first redistributed layer and the second redistributed layer.

Abstract: A display device includes: a substrate including a display area and a non-display area surrounding the display area; a light emitting element layer on the display area on the substrate and including a plurality of light emitting elements; and an encapsulating layer on the light emitting element layer and on a portion of the display area and the non-display area; and wherein the substrate comprises an upper surface on which the light emitting element layer is located, a bottom surface opposite to the upper surface, a side surface connected to the upper surface and not parallel to the upper surface, and a first inclined surface connected to the side surface and the bottom surface and not parallel to the side surface and the bottom surface, wherein an edge area of the upper surface of the substrate adjacent to an edge of the substrate, in which a processing trace remains.

Abstract: A display device and method for manufacturing thereof are provided. The display device includes a substrate having a display area and a non-display area, and including an edge, an upper surface having an edge area in which a processing trace remains adjacent to the edge, a bottom surface opposite to the upper surface, a side surface connected to the upper surface and not parallel thereto, and a first inclined surface connected to the side surface and to the bottom surface, a light-emitting element layer above the upper surface of the substrate in the display area, and including light-emitting elements, an encapsulating layer above the light-emitting element layer and corresponding to a portion of the display area and the non-display area, and a protective layer above an outer surface of the substrate, and located on at least one of the bottom surface, the side surface, or the first inclined surface.

Abstract: A display device includes: a substrate comprising an upper surface, a bottom surface facing the upper surface, and a through hole penetrating the upper surface and the bottom surface; and a light emitting element layer on the upper surface of the substrate, wherein the substrate comprises a side surface that meets the upper surface in the through hole, a first surface that meets the bottom surface, a second surface that meets the side surface, and a third surface between the first surface and the second surface, and wherein the first surface and the second surface are spaced apart from each other with the third surface therebetween, and are inclined surfaces.

Abstract: An electronic device includes a display device, which may be fabricated using a described method. The display device includes a glass substrate including a first surface, a second surface opposite the first surface, and a side surface between the first surface and the second surface, an outermost structure on the first surface of the glass substrate and located adjacent to an edge of one side of the glass substrate, and a display area including a plurality of light emitting areas on the first surface of the glass substrate and located farther from the edge of the one side of the glass substrate than the outermost structure is. A minimum distance from the side surface of the glass substrate to the outermost structure is equal to 130 ?m or less.

Abstract: An embodiment ceria-alumina support (CeO2—Al2O3 support) includes a nano-ceria having a shape of a polygonal bipyramid or a truncated polygonal bipyramid supported on alumina. An embodiment noble metal catalyst for treating exhaust gas includes a noble metal deposited on a ceria-alumina support (CeO2—Al2O3 support) that includes a nano-ceria having a shape of a polygonal bipyramid or a truncated polygonal bipyramid supported on alumina. An embodiment method for affecting resistance to sulfur-poisoning of a noble metal catalyst through structural transformation of nano-ceria supported on alumina includes performing a hydrothermal treatment of ceria supported on ?-alumina.

Abstract: The present invention relates to a gas separation membrane operation method. The method may include (a) introducing an external gas into a separation membrane module through an inlet line, (b) separating, by the separation membrane module, the external gas into a permeable gas and an impermeable gas according to permeability with respect to a separation membrane, transferring the permeable gas to the separation line, and transferring the impermeable gas to the outflow line, and (c) injecting at least a part of the impermeable gas transferred to the outflow line into an inlet of the separation membrane module.

Abstract: The present invention relates to a mini-brain structure and a construction method therefor and, more specifically, to a mini-brain and a construction method therefor, wherein induced pluripotent stem cells can be used to prepare brain organoids for different brain regions accounting for the cerebrum, the mesencephalon, the cerebellum, the thalamus, and the like and the organoids are combined into single structures, thereby making it possible to further effectively implement actual brain functions and wherein brain organoids for different brain regions can be selectively combined into single structures according to purposes, thereby achieving the aim of using brain organoids and enhancing convenience and economical benefit.

Abstract: The present invention relates to: a toll-like receptor 7 or 8 agonist-drug complex material in which a functional drug and a toll-like receptor 7 or 8 agonist are bonded by a chemical bond containing a cleavable site; and using the properties of the temporarily inactivated state, the side effects of the toll-like receptor 7 or 8 agonist can be reduced. In particular, the complex material is designed such that the immunostimulatory function of the toll-like receptor 7 or 8 agonist is inhibited due to the chemical bond, while the immunostimulatory function is recovered at an injection site or in a tumor microenvironment or target immune cells, thus exhibiting kinetic properties in which immunostimulatory efficacy can be controlled over time, and minimizing the induction of nonspecific immune responses.

Abstract: The present invention relates to: a lyophilized preparation of a pathogen cell wall skeleton, the preparation containing the pathogen cell wall skeleton as an active ingredient; various live-pathogen-mimetic nanoparticles produced by using the lyophilized preparation and antagonists of toll-like receptor 7 or 8 which can induce the efficacy of the live pathogen; a use thereof; and a production method thereof.