Abstract: Polishing apparatus and related methods employ aligned first and second magnetic field sources to adjust the compressive force and/or pressure applied by a carrier head against a target workpiece (such as a wafer) by selectively and controllably generating a repellant or attractive force between the two magnetic field sources.

Abstract: A dry cleaning apparatus for cleaning a surface of a semiconductor substrate comprises a chamber comprising a first wall and a second wall, a supporting member including a wafer receiving surface, a cleaning member for removing particles from the surface of the substrate placed on the supporting member, and a carrier gas supplying member for supplying a carrier gas and for transporting the particles separated from the surface of the substrate to the outside of the chamber, wherein the first wall of the chamber including a first portion disposed to face the wafer receiving surface and a second portion formed adjacent to the first portion and disposed to receive a part of the carrier gas supplying member.

Abstract: A dual damascene process is disclosed. According to the dual damascene process of the present invention, a first recessed region through an intermetal dielectric layer is filled with a bottom protecting layer, and the bottom protecting layer and the intermetal dielectric layer are simultaneously etched to form a second recessed region that has a shallower depth and wider width than the first recessed region on the first recessed region by using an etch gas selectively etches the intermetal dielectric layer with respect to the bottom protecting layer. In other words, the etch selectivity ratio, the intermetal dielectric layer with respect to the bottom protecting layer, is preferably about 0.5 to about 1.5. Thus, it is possible to form a dual damascene structure without the formation of a byproduct or an oxide fence.

Abstract: In a method for filling a hole with a metal, an insulating layer, a first mask layer and a second mask layer are successively formed on a semiconductor substrate. The first and second mask layers are etched using a photoresist pattern to form first and second masks. The first mask layer pattern is selectively etched using an etchant, the first mask layer pattern having a higher etching selectivity than the second layer pattern with respect to the etchant, to form a third mask layer pattern having a broadened opening. The insulating layer is etched using the second mask to form a hole in the insulating layer. A metal layer is formed in the hole and the third opening. The metal layer is planarized to form a metal plug buried in the hole without recesses or voids.

Abstract: A megasonic cleaning apparatus is provided for removing contamination particles on a wafer. The megasonic cleaning apparatus includes a piezoelectric transducer and an energy transfer rod. The piezoelectric transducer is for generating megasonic energy. The energy transfer rod installed over the wafer along a radial direction of the wafer is for distributing the megasonic energy to cleaning solution over the wafer and for vibrating the cleaning solution. The energy transfer rod is shaped and sized to uniformly distribute energy in the radial direction of the wafer through the cleaning solution to remove the contamination particles from the wafer.

Abstract: There is provided a chemical mechanical polishing apparatus, which may include a polishing table rotated by a polishing table motor and having a pad thereon, a carrier head located above the polishing table to be rotatable by the driving of a carrier head motor and having a wafer located under the bottom thereof, a slurry supplier for supplying a slurry to the upper portion of the polishing table, a first polishing end point detector for detecting a polishing end point through the temperature change of the temperature sensor, at least one temperature sensor for detecting the temperature of a polishing region (the wafer, the pad, and the slurry), and a second polishing end point detector for detecting a polishing end point from the changes of load current, voltage, and resistance of the carrier head motor.

Abstract: Disclosed herein are slurry compositions for use in CMP(chemical mechanical polishing) process of metal wiring in manufacturing semiconductor devices, comprising a peroxide, an inorganic acid, a propylenediaminetetraacetate(PDTA)-metal complex, a carboxylic acid, a metal oxide powder, and de-ionized water, wherein the PDTA-metal complex plays a major role in improving overall polishing performance and reproducibility thereof by preventing abraded tungsten oxide from readhesion onto the polished surface, as well as in improving the dispersion stability of the slurry composition.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming an interconnection line over a ssubstrate. The interconnection line functions as a first electrode. A first insulating layer is formed on the substrate including the metal interconnection line. An electrode layer and an oxide layer are formed on the first insulating layer. A photoresist pattern is formed on the oxide layer. The oxide layer and the electrode layer are etched using the photoresist pattern as an etching mask. As a result, a second electrode and an oxide layer pattern, which are stacked, are formed over the interconnection line. At least the electrode layer is etched using a wet etching technique. The photoresist pattern is then removed.

Abstract: A method of forming a via contact structure using a dual damascene technique is provided. The method includes forming a lower interconnection line on a semiconductor substrate and sequentially forming an inter-metal dielectric layer and a hard mask layer on the semiconductor substrate having the lower interconnection line. The hard mask layer and the inter-metal dielectric layer are successivley patterned to form a via hole that exposes the lower interconnnection line. A sacrificial layer filling the via hole is formed on the hard mask layer. The sacrificial layer and the hard mask layer are patterned to form a first sacrificial layer pattern having an opening that crosses over the via hole and a second sacrificial layer pattern that remains in the via hole and to simultaneously form a hard mask pattern underneath the first sacrificial layer pattern.

Abstract: In a method and apparatus for polishing a Cu metal layer and a method for forming Cu metal wiring, Cu oxide created by a surface oxidation of a Cu metal layer is removed from the wafer. The Cu metal layer, in which Cu oxide is removed, is polished. By polishing the Cu metal layer using the above method, process failures, such as scratches, caused by the presence of remnants of Cu oxide during subsequent polishing can be prevented.

Abstract: In a method and apparatus for polishing a Cu metal layer and a method for forming Cu metal wiring, Cu oxide created by a surface oxidation of a Cu metal layer is removed from the wafer. The Cu metal layer, in which Cu oxide is removed, is polished. By polishing the Cu metal layer using the above method, process failures, such as scratches, caused by the presence of remnants of Cu oxide during subsequent polishing can be prevented.

Abstract: A CMP oxide slurry includes an aqueous solution containing abrasive particles and two or more different passivation agents. Preferably, the aqueous solution is made up of deionized water, and the abrasive particles are a metal oxide selected from the group consisting of ceria, silica, alumina, titania, zirconia and germania. Also, a first passivation agent may be an anionic, cationic or nonionic surfactant, and a second passivation agent may be a phthalic acid and its salts. In one example, the first passivation agent is poly-vinyl sulfonic acid, and the second passivation agent is potassium hydrogen phthalate. The slurry exhibits a high oxide to silicon nitride removal selectivity.

Abstract: A semiconductor wafer cleaning apparatus includes a gas spraying unit, having a gas injection tube and a gas guard extending therearound, for spraying cleaning gas into a water layer formed on a wafer. The gas guard forms a small chamber just above the water layer, so that the partial pressure of gas injected from the gas injection tube is increased in the small chamber, whereupon the cleaning gas readily dissolves in the water layer. As a result, a cleaning solution having a high concentration of cleaning gas is produced, whereby the cleaning efficacy of the solution is high. Subsequently, a drying gas, such as isopropyl alcohol, for drying the wafer can be ejected onto the water layer using the gas spraying unit. Thus, the semiconductor wafer cleaning apparatus has a simple structure.

Abstract: An inductor for a system-on-a-chip and a method for manufacturing the inductor are disclosed. The inductor comprises a conductive line formed by connecting a plurality of conductive patterns grown from a seed layer formed on a lower wiring. The method comprises using an electrolytic plating process or an electroless plating process to grow the plurality of adjacent conductive patterns from the seed layer until they become connected. The method also enables adjusting the height and width of the conductive line to desired levels.

Abstract: A method of forming a metal pattern using a selective electroplating process is provided. First, a dielectric layer is formed on an underlying layer. Then, a trench defining blanket region is formed by patterning the dielectric layer. A diffusion barrier layer is conformally formed in the trench and on the blanket region. A polishing/plating stop layer and an upper seed layer are conformally formed on the diffusion barrier layer in a successive manner. The polishing/plating layer in the blanket region is exposed by selectively removing the upper seed layer in the blanket region, and, at the same time, a seed layer pattern remaining in the trenches is formed. An upper conductive layer is formed to fill the trench surrounded by the seed layer pattern using an electroplating process. Then, the dielectric layer in the blanket region is exposed by planarizing the upper conductive layer, the polishing/plating stop layer, the seed layer pattern, and the diffusion barrier layer.

Abstract: There is provided a chemical mechanical polishing apparatus, which may include a polishing table rotated by a polishing table motor and having a pad thereon, a carrier head located above the polishing table to be rotatable by the driving of a carrier head motor and having a wafer located under the bottom thereof, a slurry supplier for supplying a slurry to the upper portion of the polishing table, a first polishing end point detector for detecting a polishing end point through the temperature change of the temperature sensor, at least one temperature sensor for detecting the temperature of a polishing region (the wafer, the pad, and the slurry), and a second polishing end point detector for detecting a polishing end point from the changes of load current, voltage, and resistance of the carrier head motor.

Abstract: A semiconductor wafer cleaning apparatus includes a gas spraying unit, having a gas injection tube and a gas guard extending therearound, for spraying cleaning gas into a water layer formed on a wafer. The gas guard forms a small chamber just above the water layer, so that the partial pressure of gas injected from the gas injection tube is increased in the small chamber, whereupon the cleaning gas readily dissolves in the water layer. As a result, a cleaning solution having a high concentration of cleaning gas is produced, whereby the cleaning efficacy of the solution is high. Subsequently, a drying gas, such as isopropyl alcohol, for drying the wafer can be ejected onto the water layer using the gas spraying unit. Thus, the semiconductor wafer cleaning apparatus has a simple structure.

Abstract: Various methods are provided for forming metal interconnection layers of semiconductor devices.

Abstract: A polishing slurry including an abrasive, deionized water, a pH controlling agent, and polyethylene imine, can control the removal rates of a silicon oxide layer and a silicon nitride layer which are simultaneously exposed during chemical mechanical polishing (CMP) of a conductive layer. A relative ratio of the removal rate of the silicon oxide layer to that of the silicon nitride layer can be controlled by controlling an amount of the choline derivative.

Abstract: Embodiments of the invention include a megasonic energy cleaning apparatus that has the ability to rotate the wafer to be cleaned, as well as rotate the cleaning probe during the cleaning process. Rotating the cleaning probe while the wafer is being cleaned is effective to increase the cleaning action of the apparatus while also minimizing damage to the wafer. Curved grooves, such as a spiral groove, can be etched into the cleaning probe to minimize forming harmful waves that could potentially cause damage to the wafer surface or to structures already made on the surface. Using a cleaning probe having a curved groove while also rotating the cleaning probe effectively cleans particles from a wafer while also limiting damage to the surface of the wafer.