Patents by Inventor Sang-soo Ko
Sang-soo Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240083384Abstract: A vehicle seat reinforcement device includes a leg portion mounted on a floor panel, a seat cushion frame slidably mounted on the leg portion, and a load reinforcing structure connected between the leg portion and the seat cushion frame, wherein when a seat belt anchorage load is transferred to the seat cushion frame, the seat cushion frame is locked to the leg portion by the load reinforcing structure.Type: ApplicationFiled: February 3, 2023Publication date: March 14, 2024Applicants: Hyundai Motor Company, Kia Corporation, Daechang Seat Co.,LTD-Dongtan, Hyundai Transys Inc.Inventors: Sang Soo LEE, Chan Ho JUNG, Mu Young KIM, Sang Hark LEE, Ho Suk JUNG, Deok Soo LIM, Sang Do PARK, In Sun BAEK, Sin Chan YANG, Chan Ki CHO, Myung Soo LEE, Jae Yong JANG, Jun Sik HWANG, Ho Sung KANG, Hae Dong KWAK, Hyun Tak KO
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Patent number: 11789865Abstract: A semiconductor device is provided. The semiconductor device comprises a first memory unit including a first memory area, and a first logic area electrically connected to the first memory area, the first logic area including a cache memory and an interface port. The first memory unit executes a data transmission and reception operation with a memory unit adjacent to the first memory unit via the first interface port and the cache memory.Type: GrantFiled: December 8, 2021Date of Patent: October 17, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Soo Ko, Jae Gon Kim, Kyoung Young Kim, Sang Hyuck Ha
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Publication number: 20220100656Abstract: A semiconductor device is provided. The semiconductor device comprises a first memory unit including a first memory area, and a first logic area electrically connected to the first memory area, the first logic area including a cache memory and an interface port. The first memory unit executes a data transmission and reception operation with a memory unit adjacent to the first memory unit via the first interface port and the cache memory.Type: ApplicationFiled: December 8, 2021Publication date: March 31, 2022Inventors: SANG SOO KO, JAE GON KIM, KYOUNG YOUNG KIM, SANG HYUCK HA
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Patent number: 11200165Abstract: A semiconductor device is provided. The semiconductor device comprises a first memory unit including a first memory area, and a first logic area electrically connected to the first memory area, the first logic area including a cache memory and an interface port. The first memory unit executes a data transmission and reception operation with a memory unit adjacent to the first memory unit via the first interface port and the cache memory.Type: GrantFiled: July 30, 2019Date of Patent: December 14, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Soo Ko, Jae Gon Kim, Kyoung Young Kim, Sang Hyuck Ha
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Patent number: 10715159Abstract: A local oscillator generator (LO generator) may be configured to transmit an LO signal to a mixer. The LO generator may include an input buffer configured to generate a first internal oscillator signal based on the input oscillator signal. The LO generator may include a frequency dividing circuit configured to generate a second internal oscillator signal based on dividing a frequency of the first internal oscillator signal. The LO generator may include an output buffer configured to generate the LO signal based on the second internal oscillator signal. The input buffer and the frequency dividing circuit may each be configured to receive a power voltage independently of the output buffer.Type: GrantFiled: April 29, 2019Date of Patent: July 14, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-seog Kim, Sang-soo Ko, Byoung-joong Kang
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Publication number: 20200210836Abstract: A neural network optimizing device includes a performance estimating module that outputs estimated performance according to performing operations of a neural network based on limitation requirements on resources used to perform the operations of the neural network. A portion selecting module receives the estimated performance from the performance estimating module and selects a portion of the neural network which deviates from the limitation requirements. A new neural network generating module generates, through reinforcement learning, a subset by changing a layer structure included in the selected portion of the neural network, determines an optimal layer structure based on the estimated performance provided from the performance estimating module, and changes the selected portion to the optimal layer structure to generate a new neural network. A final neural network output module outputs the new neural network generated by the new neural network generating module as a final neural network.Type: ApplicationFiled: August 24, 2019Publication date: July 2, 2020Inventors: KYOUNG YOUNG KIM, SANG SOO KO, BYEOUNG-SU KIM, JAE GON KIM, DO YUN KIM, SANG HYUCK HA
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Publication number: 20200174928Abstract: A semiconductor device is provided. The semiconductor device comprises a first memory unit including a first memory area, and a first logic area electrically connected to the first memory area, the first logic area including a cache memory and an interface port. The first memory unit executes a data transmission and reception operation with a memory unit adjacent to the first memory unit via the first interface port and the cache memory.Type: ApplicationFiled: July 30, 2019Publication date: June 4, 2020Inventors: SANG SOO KO, JAE GON KIM, KYOUNG YOUNG KIM, SANG HYUCK HA
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Publication number: 20190253060Abstract: A local oscillator generator (LO generator) may be configured to transmit an LO signal to a mixer. The LO generator may include an input buffer configured to generate a first internal oscillator signal based on the input oscillator signal. The LO generator may include a frequency dividing circuit configured to generate a second internal oscillator signal based on dividing a frequency of the first internal oscillator signal. The LO generator may include an output buffer configured to generate the LO signal based on the second internal oscillator signal. The input buffer and the frequency dividing circuit may each be configured to receive a power voltage independently of the output buffer.Type: ApplicationFiled: April 29, 2019Publication date: August 15, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Nam-seog Kim, Sang-soo Ko, Byoung-joong Kang
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Patent number: 10326460Abstract: A local oscillator generator (LO generator) may be configured to transmit an LO signal to a mixer. The LO generator may include an input buffer configured to generate a first internal oscillator signal based on the input oscillator signal. The LO generator may include a frequency dividing circuit configured to generate a second internal oscillator signal based on dividing a frequency of the first internal oscillator signal. The LO generator may include an output buffer configured to generate the LO signal based on the second internal oscillator signal. The input buffer and the frequency dividing circuit may each be configured to receive a power voltage independently of the output buffer.Type: GrantFiled: January 12, 2018Date of Patent: June 18, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-seog Kim, Sang-soo Ko, Byoung-joong Kang
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Publication number: 20180205386Abstract: A local oscillator generator (LO generator) may be configured to transmit an LO signal to a mixer. The LO generator may include an input buffer configured to generate a first internal oscillator signal based on the input oscillator signal. The LO generator may include a frequency dividing circuit configured to generate a second internal oscillator signal based on dividing a frequency of the first internal oscillator signal. The LO generator may include an output buffer configured to generate the LO signal based on the second internal oscillator signal. The input buffer and the frequency dividing circuit may each be configured to receive a power voltage independently of the output buffer.Type: ApplicationFiled: January 12, 2018Publication date: July 19, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Nam-seog KIM, Sang-soo KO, Byoung-joong KANG
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Patent number: 8571143Abstract: A quadrature signal phase controller includes a first phase shifter and a second phase shifter. The first phase shifter generates phase shifted first in-phase differential output signals and phase shifted first quadrature-phase differential output signals. The second phase shifter generates phase shifted second in-phase differential output signals and phase shifted second quadrature-phase differential output signals. Each of the first and second phase shifters increases or decreases the phase difference between the first in-phase differential output signals and the second quadrature-phase differential output signals, and the phase difference between the second in-phase differential output signals and the first quadrature-phase differential output signals, in response to a change in a level of the first control signal and a change in a level of the second control signal.Type: GrantFiled: June 4, 2012Date of Patent: October 29, 2013Assignee: Samsung Electronics Co., Ltd.Inventor: Sang Soo Ko
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Patent number: 8446190Abstract: A frequency divider includes a prescaler and multiple modulus dividers commonly coupled to the prescaler. The prescaler generates intermediate frequency signals having a same phase difference with respect to one another in response to an oscillation frequency signal. The prescaler operates at a first frequency. The modulus dividers respectively divide the intermediate frequency signals with respective ratio to provide a plurality of division frequency signals in response to a control signal. The modulus dividers operate at a second frequency less than the first frequency.Type: GrantFiled: July 9, 2009Date of Patent: May 21, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Woogeun Rhee, Xueyi Yu, Yuanfeng Sun, Sang-Soo Ko, Byeong-Ha Park, Hyung-Ki Ahn, Woo-Seung Choo, Zhihua Wang
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Publication number: 20120243641Abstract: A quadrature signal phase controller includes a first phase shifter and a second phase shifter. The first phase shifter generates phase shifted first in-phase differential output signals and phase shifted first quadrature-phase differential output signals. The second phase shifter generates phase shifted second in-phase differential output signals and phase shifted second quadrature-phase differential output signals. Each of the first and second phase shifters increases or decreases the phase difference between the first in-phase differential output signals and the second quadrature-phase differential output signals, and the phase difference between the second in-phase differential output signals and the first quadrature-phase differential output signals, in response to a change in a level of the first control signal and a change in a level of the second control signal.Type: ApplicationFiled: June 4, 2012Publication date: September 27, 2012Inventor: Sang Soo Ko
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Patent number: 8194794Abstract: A quadrature signal phase controller includes a first phase shifter and a second phase shifter. The first phase shifter generates phase shifted first in-phase differential output signals and phase shifted first quadrature-phase differential output signals. The second phase shifter generates phase shifted second in-phase differential output signals and phase shifted second quadrature-phase differential output signals. Each of the first and second phase shifters increases or decreases the phase difference between the first in-phase differential output signals and the second quadrature-phase differential output signals, and the phase difference between the second in-phase differential output signals and the first quadrature-phase differential output signals, in response to a change in a level of the first control signal and a change in a level of the second control signal.Type: GrantFiled: November 25, 2009Date of Patent: June 5, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Sang Soo Ko
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Publication number: 20100329388Abstract: A frequency synthesizer includes a distributed phase detector circuit, a multiple charge pump, a loop filter, a voltage-controlled oscillator and a dividing circuit. The distributed phase detector circuit delays an up signal and a down signal to generate a delayed up signal and a delayed down signal. The multiple charge pump generates a distributed current signal including a plurality of current pulse signals. Each of the current pulse signal is based on each bit of the delayed up signal and the delayed down signal. The loop filter filters the distributed current signal to generate a control voltage. The voltage-controlled oscillator generates an oscillation frequency signal based on the control voltage. The dividing circuit divides the oscillation frequency signal to generate a plurality of division frequency signals in response to a plurality of control signals, where the frequency signals are fedback to the distributed phase detector circuit.Type: ApplicationFiled: April 16, 2010Publication date: December 30, 2010Inventor: Sang-Soo KO
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Publication number: 20100225361Abstract: A frequency divider includes a prescaler and multiple modulus dividers commonly coupled to the prescaler. The prescaler generates intermediate frequency signals having a same phase difference with respect to one another in response to an oscillation frequency signal. The prescaler operates at a first frequency. The modulus dividers respectively divide the intermediate frequency signals with respective ratio to provide a plurality of division frequency signals in response to a control signal. The modulus dividers operate at a second frequency less than the first frequency.Type: ApplicationFiled: July 9, 2009Publication date: September 9, 2010Applicants: SAMSUNG ELECTRONICS CO., LTD., TSINGHUA UNIVERSITYInventors: Woogeun RHEE, Xueyi YU, Yuanfeng SUN, Sang-Soo KO, Byeong-Ha PARK, Hyung-Ki AHN, Woo-Seung CHOO, Zhihua WANG
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Publication number: 20100128820Abstract: A quadrature signal phase controller includes a first phase shifter and a second phase shifter. The first phase shifter generates phase shifted first in-phase differential output signals and phase shifted first quadrature-phase differential output signals. The second phase shifter generates phase shifted second in-phase differential output signals and phase shifted second quadrature-phase differential output signals. Each of the first and second phase shifters increases or decreases the phase difference between the first in-phase differential output signals and the second quadrature-phase differential output signals, and the phase difference between the second in-phase differential output signals and the first quadrature-phase differential output signals, in response to a change in a level of the first control signal and a change in a level of the second control signal.Type: ApplicationFiled: November 25, 2009Publication date: May 27, 2010Inventor: Sang Soo KO
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Patent number: 7408419Abstract: A sigma-delta fractional-N phase locked loop has faster lock time with increased charge pump current and decreased loop filter resistance in the unlock state. On the other hand, the sigma-delta fractional-N phase locked loop has lower noise susceptibility and lower frequency error with gradual decrease in charge pump current and gradual increase in loop filter resistance, in the lock state.Type: GrantFiled: October 25, 2006Date of Patent: August 5, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Sang-Soo Ko
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Publication number: 20070164829Abstract: A sigma-delta fractional-N phase locked loop has faster lock time with increased charge pump current and decreased loop filter resistance in the unlock state. On the other hand, the sigma-delta fractional-N phase locked loop has lower noise susceptibility and lower frequency error with gradual decrease in charge pump current and gradual increase in loop filter resistance, in the lock state.Type: ApplicationFiled: October 25, 2006Publication date: July 19, 2007Inventor: Sang-Soo Ko
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Patent number: 7071869Abstract: A radar system using a quadrature signal includes a quadrature push—push oscillator for generating four harmonics with a 90-degree phase difference from each other, and producing two-balanced 2nd harmonic signals from the harmonics; a first coupler block for radiating one of the 2nd harmonics through an antenna; a second coupler block for terminating the other 2nd harmonic to ground; and a power combiner for combining a transmitted signal that is leaked from the first and second coupler blocks with the received signal that is radiated through the antenna. The radar system features an improved receiving sensitivity by offsetting the leakage signals of the sending end. Also, the radar system can be made very small by using a single antenna for transmitting and receiving.Type: GrantFiled: July 13, 2005Date of Patent: July 4, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: In-sang Song, Song-cheol Hong, Sang-soo Ko, Jeong-geun Kim, Hong-chan Kim