Patents by Inventor Sang-Su Kim
Sang-Su Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10622444Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.Type: GrantFiled: September 7, 2018Date of Patent: April 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Han Lee, Jae-Hwan Lee, Sang-Su Kim, Hwan-Wook Choi, Tae-Jong Lee, Seung-Mo Ha
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Publication number: 20200091286Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.Type: ApplicationFiled: November 25, 2019Publication date: March 19, 2020Inventors: Jung-Han LEE, Jae-Hwan LEE, Sang-Su KIM, Hwan-Wook CHOI, Tae-Jong LEE, Seung-Mo HA
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Patent number: 10566331Abstract: A semiconductor device includes: a fin-type active area extending in a first direction protruding from a substrate; a plurality of nanosheet stacked structures; a blocking film covering a part of the upper surface and one sidewall of each of a pair of nanosheet stacked structures adjacent to both sides of the fin-type active area among the plurality of nanosheet stacked structures; a gate electrode extending in a second direction intersecting the first direction on the fin-type active area, the gate electrode including a real gate electrode surrounding the plurality of nanosheets and a dummy gate electrode disposed on the blocking film; and a gate dielectric layer between the real gate electrode and the plurality of nanosheets and between the dummy gate electrode and the blocking film.Type: GrantFiled: January 25, 2019Date of Patent: February 18, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-gil Yang, Sang-su Kim, Sun-wook Kim, Geum-jong Bae, Seung-min Song, Soo-jin Jeong
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Publication number: 20200051981Abstract: A semiconductor device includes: a fin-type active area extending in a first direction protruding from a substrate; a plurality of nanosheet stacked structures; a blocking film covering a part of the upper surface and one sidewall of each of a pair of nanosheet stacked structures adjacent to both sides of the fin-type active area among the plurality of nanosheet stacked structures; a gate electrode extending in a second direction intersecting the first direction on the fin-type active area, the gate electrode including a real gate electrode surrounding the plurality of nanosheets and a dummy gate electrode disposed on the blocking film; and a gate dielectric layer between the real gate electrode and the plurality of nanosheets and between the dummy gate electrode and the blocking film.Type: ApplicationFiled: January 25, 2019Publication date: February 13, 2020Inventors: Jung-gil YANG, Sang-su KIM, Sun-wook KIM, Geum-jong BAE, Seung-min SONG, Soo-jin JEONG
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Patent number: 10411129Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.Type: GrantFiled: January 23, 2018Date of Patent: September 10, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shigenobu Maeda, Tae-Yong Kwon, Sang-Su Kim, Jae-Hoo Park
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Publication number: 20190227666Abstract: A touch screen device and a control method therefor is provided. The touch screen device includes: a touch screen which is mounted on a monitor for displaying an image input from a plurality of image interfaces, on divided screens through a divided screen synthesizer so as to receive an input touch state; a touch control unit for selecting a matching touch interface from among a plurality of touch interfaces on the basis of division information of divided screens with respect to touch coordinates input from the touch screen, and converting the touch coordinates into absolute coordinates for the matching touch interface; and a touch output unit for outputting absolute coordinates to a matching touch interface by the touch control unit.Type: ApplicationFiled: August 9, 2017Publication date: July 25, 2019Inventors: Son Ou LEE, Sang Su KIM, Tae Heon NOH, Hyeoung Kyu CHANG, IL GOOK CHO, Woo HWANGBO
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Publication number: 20190107728Abstract: The present invention relates to a stereoscopic image display through which after the incident light incident from a projector lens is split into different lights according to polarized components, by selectively delaying the phase of each split light by a predetermined value through an on/off operation of an optical switch module, each light is converted to have the same polarized component, and the synthesized light obtained by synthesizing the lights having the same polarized component is projected on a screen so as to double the luminance on the screen.Type: ApplicationFiled: March 17, 2017Publication date: April 11, 2019Inventors: Kim Hung YU, Sang Su KIM
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Publication number: 20190019864Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.Type: ApplicationFiled: September 7, 2018Publication date: January 17, 2019Inventors: Jung-Han Lee, Jae-Hwan Lee, Sang-Su Kim, Hwan-Wook Choi, Tae-Jong Lee, Seung-Mo Ha
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Patent number: 10165415Abstract: A method for performing geomagnetic signal processing using a geomagnetic signal processing apparatus is provided. The method includes obtaining a geomagnetic signal based on a geomagnetic sensor output; converting the obtained geomagnetic signal into a high frequency signal having a frequency equal to or higher than a reference frequency using a signal processing filter; extracting abnormal high frequency signal values outside a predetermined critical range from the converted high frequency signal; determining whether a sum of the extracted abnormal high frequency signal values converges into a critical range a preset time window; and correcting the geomagnetic signal based on the determining.Type: GrantFiled: October 17, 2017Date of Patent: December 25, 2018Assignee: SAMSUNG SDS CO., LTD.Inventors: Sang Su Kim, Young Wn Kwun, Jung Woo Cho, Ho Jun Lee, Young Mi Son
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Patent number: 10137533Abstract: A multi-functional apparatus for testing and etching a substrate capable of increasing spatial efficiency and manufacturing efficiency by performing testing and etching operations in a same chamber body and a substrate processing apparatus including the same, the multi-functional apparatus including a chamber body having an entrance into which the substrate is injected in one of its sides and an exit from which the substrate is ejected in another one of its sides; a transfer unit disposed inside of the chamber body and for transferring the injected substrate in a direction from the entrance to the exit; a laser etching unit disposed on an upper portion of the transfer unit and for etching a part of the substrate disposed on the transfer unit; and a testing unit for testing the substrate disposed on the transfer unit.Type: GrantFiled: May 16, 2016Date of Patent: November 27, 2018Assignee: Samsung Display Co., Ltd.Inventors: Sung-Hwan Kim, Sang-Su Kim, Byoung-Seong Jeong, Je-Hyun Song, Tae-Hun Lee, Sung-Won Yang, Tae-Hyung Kim
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Patent number: 10074717Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.Type: GrantFiled: January 12, 2016Date of Patent: September 11, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Han Lee, Jae-Hwan Lee, Sang-Su Kim, Hwan-Wook Choi, Tae-Jong Lee, Seung-Mo Ha
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Publication number: 20180151736Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.Type: ApplicationFiled: January 23, 2018Publication date: May 31, 2018Inventors: Shigenobu Maeda, Tae-Yong KWON, Sang-Su KIM, Jae-Hoo PARK
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Patent number: 9984925Abstract: A semiconductor device, including a first fin-type pattern; a first gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and including an upper portion and a lower portion; a second gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and being spaced apart from the first gate spacer; a first trench defined by the first gate spacer and the second gate spacer; a first gate electrode partially filling the first trench; a first capping pattern on the first gate electrode and filling the first trench; and an interlayer insulating layer covering an upper surface of the capping pattern, a width of the upper portion of the first gate spacer decreasing as a distance from an upper surface of the first fin-type pattern increases, and an outer sidewall of the upper portion of the first gate spacer contacting the interlayer insulating layer.Type: GrantFiled: June 14, 2016Date of Patent: May 29, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Ho Jeon, Sang-Su Kim, Cheol Kim, Yong-Suk Tak, Myung-Geun Song, Gi-Gwan Park
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Patent number: 9978835Abstract: A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel region, a gate that surrounds at least a part of the channel region, and a gate dielectric film that is disposed between the channel region and the gate. A source/drain region that contacts one end of the at least one nanowire is formed in a semiconductor layer that extends from the substrate to the one end of the at least one nanowire. Insulating spacers are formed between the substrate and the at least one nanowire. The insulating spacers are disposed between the gate and the source/drain region and are formed of a material that is different from a material of the gate dielectric film.Type: GrantFiled: October 31, 2016Date of Patent: May 22, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Gil Yang, Sang-Su Kim, Sung-Gi Hur
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Publication number: 20180115874Abstract: A method for performing geomagnetic signal processing using a geomagnetic signal processing apparatus is provided. The method includes obtaining a geomagnetic signal based on a geomagnetic sensor output; converting the obtained geomagnetic signal into a high frequency signal having a frequency equal to or higher than a reference frequency using a signal processing filter; extracting abnormal high frequency signal values outside a predetermined critical range from the converted high frequency signal; determining whether a sum of the extracted abnormal high frequency signal values converges into a critical range a preset time window; and correcting the geomagnetic signal based on the determining.Type: ApplicationFiled: October 17, 2017Publication date: April 26, 2018Applicant: SAMSUNG SDS CO., LTD.Inventors: Sang Su KIM, Young Wn KWUN, Jung Woo CHO, Ho Jun LEE, Young Mi SON
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Patent number: 9893186Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.Type: GrantFiled: July 29, 2016Date of Patent: February 13, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Shigenobu Maeda, Tae-Yong Kwon, Sang-Su Kim, Jae-Hoo Park
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Patent number: 9646891Abstract: Example embodiments relate to a metal-oxide semiconductor field effect transistor (MOSFET) of a high performance operating with a necessary threshold voltage while including a channel region formed based on a group III-V compound, and a method of manufacturing the MOSFET. The MOSFET includes a substrate, a semiconductor layer including a group III-V compound on the substrate, and a gate structure disposed on the semiconductor layer, and including a gate electrode formed based on metal and undergone an ion implantation process.Type: GrantFiled: January 26, 2015Date of Patent: May 9, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-gil Yang, Tae-yong Kwon, Xingui Zhang, Sang-su Kim
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Patent number: 9627273Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first nanowire extending through a first gate electrode and between first source and drain regions. The second transistor includes a second nanowire extending through a second gate electrode and between a second source and drain regions. The first nanowire has a first size in a first direction and a second size in a second direction, and the second nanowire has a second size in the first direction and substantially the second size in the second direction. The first nanowire has a first on current and the second nanowire has a second on current. The on current of the first nanowire may be substantially equal to the on current of the second nanowire based on a difference between the sizes of the first and second nanowires. In another arrangement, the on currents may be different.Type: GrantFiled: December 9, 2015Date of Patent: April 18, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Sang-Su Kim
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Publication number: 20170103916Abstract: A semiconductor device, including a first fin-type pattern; a first gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and including an upper portion and a lower portion; a second gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and being spaced apart from the first gate spacer; a first trench defined by the first gate spacer and the second gate spacer; a first gate electrode partially filling the first trench; a first capping pattern on the first gate electrode and filling the first trench; and an interlayer insulating layer covering an upper surface of the capping pattern, a width of the upper portion of the first gate spacer decreasing as a distance from an upper surface of the first fin-type pattern increases, and an outer sidewall of the upper portion of the first gate spacer contacting the interlayer insulating layer.Type: ApplicationFiled: June 14, 2016Publication date: April 13, 2017Inventors: Yong-Ho JEON, Sang-Su KIM, Cheol KIM, Yong-Suk TAK, Myung-Geun SONG, Gi-Gwan PARK
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Patent number: 9576955Abstract: Semiconductor devices are provided. The semiconductor devices include active fins including a buffer layer disposed on a substrate and a channel layer disposed on the buffer layer and having a first second lattice constant higher than a lattice constant of the buffer layer, a gate structure covering the channel layer and intersecting the active fins, sidewall spacers disposed on both sidewalls of the gate structure, and capping layers disposed to contact lower surfaces of the sidewall spacers and having a width substantially the same as a width of the lower surfaces of the sidewall spacers.Type: GrantFiled: January 11, 2016Date of Patent: February 21, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jae Hwan Lee, Tae Yong Kwon, Sang Su Kim, Chang Jae Yang, Jung Han Lee, Hwan Wook Choi, Yeon Cheol Heo, Sang Hyuk Hong