Abstract: A fashion accessory tool that can transform a piece of fabric. The fashion accessory tool allows a piece of fabric to be secured to a garment and adjusted after it has been secured to the garment. The piece of fabric can be woven through the fashion accessory tool and then secured in the tool with deformable features. The fashion accessory tool can be pinned to a garment and the fabric can be adjusted and styled after the fashion accessory tool is pinned.

Abstract: Instructions to be executed by a processing system are fetched from a memory. Respective age tags are assigned to the instructions such that each of the age tags indicates an age of the corresponding instruction in the processing system. A respective physical register is allocated to each destination logical register referenced by each instruction. The respective age tags assigned to the instructions are written to respective physical registers allocated to the destination logical registers of the instructions, and to a buffer configured to maintain a program order of the instructions. The instructions are executed by the processing system. Executing the instructions includes executing at least some of the instructions in an order different from the program order of the instructions. The age tags in the buffer are used to retire executed instructions in a same order as the program order of the instructions.

Abstract: An integrated circuit is provided. The integrated circuit includes a mapping circuit configured to determine a state associated with a first universal series bus (USB) communication mode based on one or both of a signal level on a first data line and a signal level on a second data line. The integrated circuit also includes a line state converter circuit configured to generate a line state associated with a second USB communication mode based on the determined state and based on one or both of the signal level on the first data line and the signal level on the second data line.

Abstract: An integrated circuit is provided. The integrated circuit includes a communication-mode determination circuitry configured to detect a signal level at one or both of a first data line and a second data line and to determine whether a communication mode of the first data line and the second data line is a first universal series bus (USB) communication mode or a second USB communication mode. The integrated circuit also includes a first transceiver circuitry configured to operate in one of multiple modes, based on the communication mode determined. The integrated circuit also includes a second transceiver circuitry configured to operate in one of multiple modes, based on the communication mode determined. A maximum signal level of the first USB communication mode is greater than a maximum signal level of the second USB communication mode.

Abstract: In a method of executing instructions in a processing system, respective global age tags are assigned to each of the one or more instructions fetched for processing by the processing system. Each global age tag indicates an age of the corresponding instruction in the processing system. Respective physical registers in a physical register file are allocated to each destination logical register referenced by each instruction. The respective global age tags are written to the in respective physical registers allocated to the destination logical registers of the instructions. The instructions are executed by the processing system. At least some of the instructions are executed in an order different from a program order of the instructions.

Abstract: An integrated circuit is provided. The integrated circuit includes a mapping circuit configured to determine a state associated with a first universal series bus (USB) communication mode based on one or both of a signal level on a first data line and a signal level on a second data line. The integrated circuit also includes a line state converter circuit configured to generate a line state associated with a second USB communication mode based on the determined state and based on one or both of the signal level on the first data line and the signal level on the second data line.

Abstract: An integrated circuit is provided. The integrated circuit includes a communication-mode determination circuitry configured to detect a signal level at one or both of a first data line and a second data line and to determine whether a communication mode of the first data line and the second data line is a first universal series bus (USB) communication mode or a second USB communication mode. The integrated circuit also includes a first transceiver circuitry configured to operate in one of multiple modes, based on the communication mode determined. The integrated circuit also includes a second transceiver circuitry configured to operate in one of multiple modes, based on the communication mode determined. A maximum signal level of the first USB communication mode is greater than a maximum signal level of the second USB communication mode.

Abstract: In some implementations, a built-in self-test (BIST) circuitry of a memory device is configured to perform an execution of a test sequence to test the memory device, wherein performing the execution comprises generating addresses of the memory device in accordance with the test sequence and advancing a value of a modulo counter as each of the addresses is generated, enable error logging when a generated address and a value of the modulo counter corresponding to the generated address match an address and a value of the modulo counter stored for a previously detected error, detect an error in data read from the memory device after enabling error logging, and store information associated with the detected error.

Abstract: A fashion accessory tool that can transform a piece of fabric. The fashion accessory tool allows a piece of fabric to be secured to a garment and adjusted after it has been secured to the garment. The piece of fabric can be woven through the fashion accessory tool and then secured in the tool with deformable features. The fashion accessory tool can be pinned to a garment and the fabric can be adjusted and styled after the fashion accessory tool is pinned.

Abstract: A fashion accessory tool that can transform a piece of fabric. The fashion accessory tool allows a piece of fabric to be secured to a garment and adjusted after it has been secured to the garment. The piece of fabric can be woven through the fashion accessory tool and then secured in the tool with deformable features. The fashion accessory tool can be pinned to a garment and the fabric can be adjusted and styled after the fashion accessory tool is pinned.

Abstract: A fashion accessory tool that can transform a piece of fabric. The fashion accessory tool allows a piece of fabric to be secured to a garment and adjusted after it has been secured to the garment. The piece of fabric can be woven through the fashion accessory tool and then secured in the tool with deformable features. The fashion accessory tool can be pinned to a garment and the fabric can be adjusted and styled after the fashion accessory tool is pinned.

Abstract: A memory system including a plurality of ports and a memory core having a plurality of memory banks. Access requests received at the ports are broadcast to the memory banks. Multiple memory banks may be concurrently accessed in response to access requests received on different ports. A memory controller provides the access requests to the memory system, and ensures that a single memory bank is not concurrently accessed by different ports. All access requests are processed with the same latency. If the memory banks include memory cells that must be periodically refreshed, then the memory controller also provides refresh requests to the memory banks. Because multiple memory banks may be concurrently accessed in response to access requests provided on different ports, the memory banks can operate at a lower frequency than the ports.

Abstract: A memory system including a plurality of ports and a memory core having a plurality of memory banks. Access requests received at the ports are broadcast to the memory banks. Multiple memory banks may be concurrently accessed in response to access requests received on different ports. A memory controller provides the access requests to the memory system, and ensures that a single memory bank is not concurrently accessed by different ports. All access requests are processed with the same latency. If the memory banks include memory cells that must be periodically refreshed, then the memory controller also provides refresh requests to the memory banks. Because multiple memory banks may be concurrently accessed in response to access requests provided on different ports, the memory banks can operate at a lower frequency than the ports.

Abstract: Write check bits are generated in a predictive manner for partial-word write transactions in a memory system implementing error code correction. A read data word and associated read check bits are read from an address of the memory. If an error exists in a byte of the read data word, this byte is identified. At the same time, one or more bytes of the uncorrected read data word are merged with one or more bytes of a write data word, thereby creating a merged data word. Write check bits are generated in response to the merged data word. If the merged data word includes a byte of the read data word, which contains an error, the write check bits are modified to reflect this error. The merged data word and the modified (or unmodified) write check bits are then written to the address of the memory.

Abstract: A memory system with transparent error correction circuitry provides full stuck-at fault coverage for both test data patterns and the corresponding error correction code (ECC) values. The memory system includes a semiconductor memory having a memory array, a memory interface and an error detection/correction unit. The memory array is configured to store test data patterns and corresponding error correction code (ECC) values. The memory interface is configured such that the ECC values are not directly accessible. The error detection/correction unit is configured to correct single-bit errors in the test data patterns and corresponding ECC values. A set of test data patterns associated with the semiconductor memory is selected such that any multiple-bit error in a test data pattern and the corresponding ECC value causes the error detection/correction unit to provide an output data pattern having an error, thereby rendering multiple-bit faults 100% detectable.

Abstract: The present invention relates to a hair drier with a 3-Dimensional control interface, comprising a housing, a control button, a power supply, a heating element and a control circuit. An electrical connection is set among the power supply, the heating element and the control circuit. The control button has a 3-D control interface and can control each functional element of the hair drier separately or synchronously. This hair drier is single-key controlled and various functions of the hair drier can be realized by easily changing the angle of the button to a different direction, or moving the button towards different directions. This hair drier is simple in structure, easy to operate and convenient to use.

Abstract: The invention describes novel nitrosated and/or nitrosylated prostaglandins, and novel compositions comprising at least one nitrosated and/or nitrosylated prostaglandin, and, optionally, at least one compound that donates, transfers or releases nitric oxide, elevates endogenous levels of endothelium-derived relaxing factor, stimulates endogenous synthesis of nitric oxide or is a substrate for nitric oxide synthase, and/or at least one vasoactive agent. The invention also provides novel compositions comprising at least one prostaglandin and at least one S-nitrosothiol compound, and, optionally, at least one vasoactive agent. The prostaglandin is preferably a prostaglandin E1 compound, more preferably alprostadil, and the S-nitrosothiol compound is preferably S-nitrosoglutathione.

Abstract: The present invention describes novel nitrosated and/or nitrosylated cyclooxygenase 2 (COX-2) inhibitors and novel compositions comprising at least one nitrosated and/or nitrosylated cyclooxygenase 2 (COX-2) inhibitor, and, optionally, at least one compound that donates, transfers or releases nitric oxide, stimulates endogenous synthesis of nitric oxide, elevates endogenous levels of endothelium-derived relaxing factor or is a substrate for nitric oxide synthase, and/or optionally, at least one therapeutic agent. The present invention also provides novel compositions comprising at least one parent COX-2 inhibitor and at least one nitric oxide donor, and, optionally, at least one therapeutic agent.

Abstract: Nonsteroidal antiinflammatory drugs which have been substituted with a nitrogen monoxide group; compositions comprising (i) a nonsteroidal antiinflammatory drug, which can optionally be substituted with a nitrogen monoxide group and (ii) a compound that directly donates, transfers or releases a nitrogen monoxide group (preferably as a charged species, particularly nitrosonium); and methods of treatment of inflammation, pain, gastrointestinal lesions and/or fever using the compositions are disclosed. The compounds and compositions protect against the gastrointestinal, renal and other toxicities that are otherwise induced by nonsteroidal antiinflammatory drugs.

Abstract: A programmable gain amplifier with three stages uses fine steps, has a large gain range, and is monotonic. The first stage comprises several amplifiers, each including a resistive feedback loop. The feedback loop comprises a series of resistors, with each resistor acting as a tap. Since the number of resistors in the loop is unchanging, monotonicity and stability is guaranteed when resistance is increased using successive taps. A switch system connects two taps at a time to an interpolation stage. Each of these taps corresponds to a specific resistor level, and thus a gain level. The interpolation stage uses a plurality of current sources inside a feedback amplifier to control the interpolation, in order to provide fine gain steps.