Abstract: A semiconductor device and manufacturing process therefor is provided in which angled dopant implantation is followed by the formation of vertical trenches in the silicon on insulator substrate adjacent to the sides of the semiconductor gate. A second dopant implantation in the exposed the source/drain junctions is followed by a rapid thermal anneal that forms the semiconductor channel in the substrate. Contacts having inwardly curved cross-sectional widths in the semiconductor substrate are then formed which connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.

Abstract: A method for forming an electrostatic discharge device using silicon-on-insulator technology is described. An N-well is formed within a silicon semiconductor substrate. A P+ region is implanted within a portion of the N-well and an N+ region is implanted within a portion of the semiconductor substrate not occupied by the N-well. An oxide layer is formed overlying the semiconductor substrate and patterned to form openings to the semiconductor substrate. An epitaxial silicon layer is grown within the openings and overlying the oxide layer. Shallow trench isolation regions are formed within the epitaxial silicon layer extending to the underlying oxide layer. Gate electrodes and associated source and drain regions are formed in and on the epitaxial silicon layer between the shallow trench isolation regions. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions.

Abstract: A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions.

Abstract: A new process for fabricating an alternating phase-shifting photomask having an alignment monitor is described. An opaque layer is provided overlying a substrate. The opaque layer is patterned to provide a mask pattern. A phase-shifting pattern is formed on the substrate wherein a portion of the phase-shifting pattern comprises an alignment monitor whereby alignment between the mask pattern and the phase-shifting pattern can be tested.

Abstract: A method for forming an electrostatic discharge device using silicon-on-insulator technology is described. An N-well is formed within a silicon semiconductor substrate. A P+ region is implanted within a portion of the N-well and an N+ region is implanted within a portion of the semiconductor substrate not occupied by the N-well. An oxide layer is formed overlying the semiconductor substrate and patterned to form openings to the semiconductor substrate. An epitaxial silicon layer is grown within the openings and overlying the oxide layer. Shallow trench isolation regions are formed within the epitaxial silicon layer extending to the underlying oxide layer. Gate electrodes and associated source and drain regions are formed in and on the epitaxial silicon layer between the shallow trench isolation regions. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions.

Abstract: A triple layered low dielectric constant material dual damascene metallization process is described. Metal lines are provided covered by an insulating layer overlying a semiconductor substrate. A first dielectric layer of a first type is deposited overlying the insulating layer. A second dielectric layer of a second type is deposited overlying the first dielectric layer. A via pattern is etched into the second dielectric layer. Thereafter, a third dielectric layer of the first type is deposited overlying the patterned second dielectric layer. Simultaneously, a trench pattern is etched into the third dielectric layer and the via pattern is etched into the first dielectric layer to complete the formation of dual damascene openings in the fabrication of an integrated circuit device. If the first type is a low dielectric constant organic material, the second type will be a low dielectric constant inorganic material.

Abstract: A method for forming an electrostatic discharge device using silicon-on-insulator technology is described. A silicon-on-insulator substrate is provided comprising a semiconductor substrate underlying an oxide layer underlying a silicon layer. The silicon layer and oxide layer are patterned to form a gate electrode wherein the semiconductor substrate is exposed. Ions are implanted into the exposed semiconductor substrate to form source and drain regions adjacent to the gate electrode. Spacers are formed on sidewalls of the gate electrode. An interlevel dielectric layer is deposited overlying the gate electrode. Openings are formed through the interlevel dielectric layer to the source and drain regions and filled with a conducting layer. The conducting layer is patterned to form conducting lines to complete formation of an electrostatic discharge device using SOI technology in the fabrication of integrated circuits.

Abstract: A semiconductor device and manufacturing process therefor is provided in which angled dopant implantation is followed by the formation of vertical trenches in the silicon on insulator substrate adjacent to the sides of the semiconductor gate. A second dopant implantation in the exposed the source/drain junctions is followed by a rapid thermal anneal which forms the semiconductor channel in the substrate. Contacts are then formed which connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.

Abstract: A method of patterning a hard mask, the comprising the following steps. A semiconductor structure is provided. A conductor film is formed over the semiconductor structure. An oxide layer is formed over the conductor film. A patterned metal oxide layer is formed over the conductor film. The oxide layer and the conductor film are etched, using the metal oxide layer as a hard mask, to form a patterned structure.

Abstract: An integrated microelectronics semiconductor circuit fabricated on a silicon-on-insulator (SOI) type substrate can be protected from unwanted current surges and excessive heat buildup during fabrication by means of a heat-dissipating, protective plasma-induced-damage (PID) diode. The present invention fabricates such a protective diode as a part of the overall scheme in which the transistor devices are formed.

Abstract: An integrated microelectronics semiconductor circuit fabricated on a silicon-on-insulator (SOI) type substrate can be protected from unwanted current surges and excessive heat buildup during fabrication by means of a heat-dissipating, protective plasma-induced-damage (PID) diode. The present invention fabricates such a protective diode as a part of the overall scheme in which the transistor devices are formed.

Abstract: A method of fabricating an SOI transistor device comprises the following steps. a silicon semiconductor structure is provided. A silicon oxide layer is formed over the silicon semiconductor structure. A silicon-on-insulator layer is formed over the oxide layer. A well is implanted in the silicon-on-insulator layer. A gate oxide layer is grown over the silicon-on-insulator layer. A polysilicon layer is deposited over the gate oxide layer. The polysilicon layer, gate oxide layer, and silicon oxide layer are patterned and etched to form trenches. The trenches are filled with an isolation material to at least a level even with a top surface of the polysilicon layer to form raised shallow trench isolation regions (STIs). The polysilicon layer is patterned and the non-gate portions are removed polysilicon adjacent the raised STIs forming a gate conductor between the raised STIs with the gate conductor and said raised STIs having exposed sidewalls.

Abstract: A new method of fabricating a sub-quarter micron MOSFET device is achieved. A semiconductor substrate is provided. Isolation regions are formed in this substrate. An oxide layer is provided overlying both the substrate and the isolation regions. The oxide layer is patterned and etched exposing two regions of the substrate. A selective epitaxial growth (SEG) is performed with in situ doping covering the two exposed substrate regions formed during the previous step. The doped SEG regions will form the source and drain contact regions of the MOSFET. The oxide layer region between the two doped SEG regions is then patterned and etched away exposing the substrate. This is followed by a gate oxide formation and either a polysilicon or metal gate deposition. Planarization is then performed on the surface to facilitate interconnection later in the process and to form the final gate structure.

Abstract: A method for fabricating a metal-oxide-metal capacitor is described. A first insulating layer is provided overlying a semiconductor substrate. A barrier metal layer and a first metal layer are deposited over the insulating layer. A titanium layer is deposited overlying the first metal layer. The titanium layer is exposed to an oxidizing plasma while simultaneously a portion of the titanium layer where the metal-oxide-metal capacitor is to be formed is exposed to light whereby the portion of the titanium layer exposed to light reacts with the oxidizing plasma to form titanium oxide. Thereafter, the titanium layer is removed, leaving the titanium oxide layer where the metal-oxide-metal capacitor is to be formed. A second metal layer is deposited overlying the first metal layer and the titanium oxide layer.

Abstract: A method of fabricating a transistor, comprising the following steps. A silicon semiconductor structure having spaced, raised, wedge-shaped dielectric isolation regions defining an active region there between is provided. Epitaxial silicon is grown over the active area to form an SEG region. A dummy gate is formed over the SEG region. Raised epitaxial silicon layers are grown over the SEG region adjacent the dummy gate. The dummy gate is removed, exposing the interior side walls of the raised epitaxial silicon layers. Sidewall spacers are formed on the exposed sidewalls of the raised epitaxial silicon layers. A gate oxide layer is grown over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. A layer of polysilicon is deposited over the structure and is planarized to form a gate conductor over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. The sidewall spacers are removed.

Abstract: A method of fabricating a dual damascene interconnect structure in a semiconductor device, comprises the following steps. A first level via photo sensitive dielectric layer is deposited and exposed over a semiconductor structure. A first level trench photo sensitive dielectric layer is deposited and exposed over the first via photo sensitive dielectric layer. The exposed first level via photo sensitive dielectric and trench photo sensitive dielectric layers are patterned and etched to form a first level dual damascene opening. The first level dual damascene opening comprises an integral first level via and metal line openings. A first level metal layer is deposited over the first level trench photo sensitive dielectric layer, filling the first level dual damascene opening. The first level metal layer is planarized to form at least one first level dual damascene interconnect having a first level horizontal metal line and a first level vertical via stack.

Abstract: A method of forming thick and thin gate oxides comprising the following steps. A silicon semiconductor substrate having first and second active areas separated by shallow isolation trench regions is provided. Oxide growth is selectively formed over the first active area by UV oxidation to form a first gate oxide layer having a first predetermined thickness. The first and second active areas are then simultaneously oxidized whereby the first predetermined thickness of the first gate oxide layer is increased to a second predetermined thickness and a second gate oxide layer having a predetermined thickness is formed in the second active area. The second predetermined thickness of the first oxide layer in the first active area is greater than the predetermined thickness of the second oxide layer in the second active area.

Abstract: A new method of fabricating a MOSFET device is described. A semiconductor substrate is provided and isolation areas are formed isolating active areas in the substrate. An oxide layer is provided overlying both the substrate and isolation area and is patterned and etched to expose two areas within an isolated active area of the substrate. Selective epitaxial growth (SEG) using intrinsic silicon is performed to fill the exposed substrate areas formed in the previous etch step. The oxide layer region in the active area between the two epitaxially grown silicon regions is then etched, exposing the substrate. This is followed by a gate oxide growth and a polysilicon deposition. Planarization is then performed on the surface to expose the two epitaxially grown silicon regions. A second oxide is grown consuming some of the polysilicon gate and the epitaxially grown silicon.

Abstract: A method of fabricating a MOS device having raised source/drain, raised isolation regions having isolation spacers, and a gate conductor having gate spacers is achieved. A layer of gate silicon oxide is grown over the surface of a semiconductor structure. A polysilicon layer is deposited overlying the gate silicon oxide layer. The polysilicon layer, gate silicon oxide layer and semiconductor structure are patterned and etched to form trenches. The trenches are filled with an isolation material to at least a level even with a top surface of the polysilicon layer to form raised isolation regions. The remaining polysilicon layer is patterned to remove polysilicon adjacent the raised isolation regions forming a gate conductor between the raised isolation regions. The gate conductor and the raised isolation regions having exposed sidewalls. The gate oxide layer between the gate conductor and raised isolation regions is removed.