Patents by Inventor Sang Yeon Kim
Sang Yeon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6890822Abstract: A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region.Type: GrantFiled: February 13, 2003Date of Patent: May 10, 2005Assignee: SilTerra Malaysia Sdn. Bhd.Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Ong Boon Teong, Oh Choong Young, Ng Chun Leng, Joung Joon Ho
-
Patent number: 6818514Abstract: A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact.Type: GrantFiled: February 26, 2003Date of Patent: November 16, 2004Assignee: SilTerra Malaysia Sdn. Bhd.Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Chiew Sin Ping, Wan Gie Lee, Choong Shiau Chien, Zadig Lam, Hitomi Watanabe, Naoto Inoue
-
Publication number: 20040215682Abstract: An apparatus for removing aliasing of an inverse mapping algorithm includes a tap delay unit for sequentially delaying input data; a coefficient updating unit for multiplying a selected filter coefficient to preceding data inputted to the tap delay unit and subsequent data outputted through the tap delay unit according to a range of a re-sampling interval and outputting them; an adding unit for adding output values of the coefficient updating unit and outputting them; and an interpolating unit for interpolating data outputted from the adding unit and outputting re-sampled data. Aliasing that may be generated when a warping is performed to correct optical distortion can be removed to enhance a picture quality.Type: ApplicationFiled: April 21, 2004Publication date: October 28, 2004Inventor: Sang Yeon Kim
-
Publication number: 20040166698Abstract: A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact.Type: ApplicationFiled: February 26, 2003Publication date: August 26, 2004Applicant: SilTerra Malaysia Sdn. Bhd.Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Chiew Sin Ping, Wan Gie Lee, Choong Shiau Chien, Zadig Lam, Hitomi Watanabe, Naoto Inoue
-
Publication number: 20040161897Abstract: A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region.Type: ApplicationFiled: February 13, 2003Publication date: August 19, 2004Applicant: SilTerra Malaysia Sdn. Bhd.Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Ong Boon Teong, Oh Choong Young, Ng Chun Leng, Joung Joon Ho
-
Publication number: 20040156558Abstract: Disclosed is an image warping method and apparatus thereof, by which simplified scanline algorithm is implemented by a backward transformation method with minimized implementation costs and which enables to correct image distortion of a display device such as projection TV, projector, monitor, and the like due to optical or mechanical distortion. The present invention implements scanline algorithm as follows. After a position ‘u’ of the source image has been found using the value of ‘x’ of the target image, data of the position ‘u’ of the source image is mapped to a position ‘x’ of the target image. After a position ‘v’ of the source image has been found using the values of ‘x’ and ‘y’ of the target image, data of the position ‘v’ is brought to be mapped to a position ‘y’ of the target image.Type: ApplicationFiled: February 3, 2004Publication date: August 12, 2004Inventor: Sang Yeon Kim
-
Publication number: 20040147090Abstract: A method for forming an isolation structure on a semiconductor substrate includes opening a portion of a pad oxide layer overlying the substrate using a process gas including an etchant gas and a polymer-forming gas. A portion of the substrate exposed by the opening step is etched to form a trench having a first slope and a second slope. The first slope is greater than 45 degrees, and the second slope is less than 45 degrees. The trench is filled to form the isolation structure.Type: ApplicationFiled: January 23, 2003Publication date: July 29, 2004Applicant: SilTerra Malaysia Sdn. Bhd.Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Ch?apos;ng Toh Ghee, Ramakrishnan Rajagopal, Chiew Sin Pin, Wan Gie Lee, Choong Shiau Chien, Charlie Tay, Chang Gi Lee, Hitomi Watanabe, Naoto Inoue
-
Patent number: 6700628Abstract: A device and method for controlling a brightness of an image signal in a moving picture transmission/reception system is disclosed. The present invention includes a control point detecting unit for receiving an image, calculating a Cumulative Density Function from two most significant bits of the image, dividing an axis into a required number of portions, and detecting a required number of control points. The present invention also includes an image signal brightness controlling unit for calculating and dividing six least significant bits of the image and a signal from the control point detecting unit for controlling a next frame of the image.Type: GrantFiled: May 8, 2000Date of Patent: March 2, 2004Assignee: LG Electronics Inc.Inventor: Sang Yeon Kim
-
Patent number: 6690429Abstract: A device and method for processing a color signal which can improve the sharpness of a color signal is disclosed. In the present invention, an edge of an image is detected and the detected edge is improved by making a sharp transition without over shoot or under shoot. Particularly, the color signal is delayed, and either a maximum or minimum value of the delayed signal is selectively output if the input signal is determined to be for a position at the edge region.Type: GrantFiled: February 4, 2000Date of Patent: February 10, 2004Assignee: LG Electronics Inc.Inventor: Sang Yeon Kim
-
Patent number: 6674404Abstract: A method for detecting and correcting a defective pixel in an image sensor including an M(row line)×N(column line) unit pixels, M and N being positive integers, includes a first step of electrically scanning photoelectric charges generated from unit pixels of a first row line for a first integration time and storing a first data corresponding to the photoelectric charges, a second step of electrically scanning photoelectric charges generated from the unit pixels of the first row line for a second integration time and storing a second data corresponding to the photoelectric charges, a third step of comparing the first data and the second data one another, if the first data is different from the second data, an error signal is generated and then a corresponding address of the unit pixel is stored as a defective pixel address, a fourth step of repeating the first to the third step to an Mth line by increasing an address by one, and a fifth step of comparing an address of a unit pixel to be read with the deType: GrantFiled: December 28, 1999Date of Patent: January 6, 2004Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Suk-Joong Lee, Sang-Yeon Kim
-
Patent number: 6633342Abstract: An apparatus and method for eliminating noise of a received image and compensating its sharpness is provided. A common circuit is used in a structure for eliminating noise based on a double smoothing method and a structure for making the outline sharp based on an unsharp masking method. Noise elimination and sharpness enhancement are processed for a difference signal between an original signal of the image and its low pass filtered signal, thereby compensating the original signal. Thus, an image having an improved picture quality can be provided in a product which transmits/receives or displays image data, and high competitiveness of the product can be obtained by simplifying the user interface.Type: GrantFiled: January 12, 2001Date of Patent: October 14, 2003Assignee: LG Electronics Inc.Inventor: Sang Yeon Kim
-
Publication number: 20030135528Abstract: A filter, in particular, a finite impulse response (FIR) filter having a variable data input and output rate is disclosed. The FIR filter includes a first-in first-out (FIFO) architectural buffer, an address generator for circularly generating respective addresses for FIFO of data items and providing the addresses to the buffer, a filter for performing filtering on data items having different rates, which are input from the buffer, and outputting one or more data, and a controller for controlling address generation of the address generator and controlling transfer paths of data items for filtering of the filter. It is possible to variably control the input and output rate of filtering data by the FIR filter.Type: ApplicationFiled: December 18, 2002Publication date: July 17, 2003Applicant: LG Electronics Inc.Inventors: Jong In Choi, Sang Yeon Kim, Dong Il Han
-
Patent number: 6531742Abstract: A CMOS device and a method for fabricating the same, is disclosed, the device including an insulating film formed on a substrate, first and second sapphire patterns formed on the insulating film at fixed intervals, first and second epitaxial semiconductor layers formed on the first and second sapphire patterns, isolating structures formed at edges of the first and second semiconductor layers, respectively, first and second trenches formed down to predetermined depths from surfaces of the first and second semiconductor layers, sidewall spacer structures formed at both sides of the first and second trenches, a gate insulating film formed on a surface of each of the first and second semiconductor layers between the sidewall spacer structures, first and second gate electrodes formed in the first and second trenches respectively on the gate insulating film, first conductivity type impurity regions formed in the first semiconductor layer on both sides of the first gate electrodes, and second conductivity type impurType: GrantFiled: December 26, 2000Date of Patent: March 11, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Sang Yeon Kim
-
Publication number: 20020126900Abstract: Disclosed is an image interpolation method and apparatus thereof. The present invention includes the steps of searching an edge direction to be used for interpolation by a pixel matching using input pixels and generating a pixel to be substantially interpolated by referring to pixels located on the searched edge direction. The present invention includes the steps of carrying out a first interpolation on input pixels using linear interpolation and finding weighted value coefficients in accordance with a relationship between the first interpolated pixel and the adjacent input pixels to be used for interpolation and preparing a pixel to be substantially interpolated by adaptive weighted interpolation applying the found weighted value coefficient to the adjacent input pixels. Accordingly, the present invention minimizes the blurring and is free of geometrical distortion.Type: ApplicationFiled: January 4, 2002Publication date: September 12, 2002Inventor: Sang Yeon Kim
-
Publication number: 20020012390Abstract: An apparatus and method for generating finite impulse response (FIR) filter coefficients are presented. The apparatus includes an address generator that multiplies a desired cutoff frequency f by an integer n to generate an address, a first look-up table that generates a sine function value of the address, a divider that divides the sine function value by n*pi, a multipexer that generates an impulse response function value by selecting one of a value produced from the divider and 2*f based on an outside control signal, and a multiplier that multiplies the impulse response function value by a corresponding window function value to generate an nth filter coefficient for the FIR filter.Type: ApplicationFiled: June 22, 2001Publication date: January 31, 2002Inventor: Sang Yeon Kim
-
Publication number: 20010046318Abstract: Image data fed from an image sensor having a color pixel array by 2 dimensional compression and difference algorithm is disclosed. Firstly, the red, green and blue(R/G/B) color values from the image data extracted; vertical difference color values between current R/G/B color values of a current line and previous R/G/B color values of a previous line are calculated; the vertical difference color values with a predetermined loss value are calculated to obtain quota color values; and the horizontal difference color values between a current quota color value and a previous quota color value are estimated.Type: ApplicationFiled: December 29, 2000Publication date: November 29, 2001Inventors: Suk-Joong Lee, Sang-Yeon Kim
-
Publication number: 20010038130Abstract: A CMOS device and a method for fabricating the same, is disclosed, the device including an insulating film formed on a substrate, first and second sapphire patterns formed on the insulating film at fixed intervals, first and second epitaxial semiconductor layers formed on the first and second sapphire patterns, isolating structures formed at edges of the first and second semiconductor layers, respectively, first and second trenches formed down to predetermined depths from surfaces of the first and second semiconductor layers, sidewall spacer structures formed at both sides of the first and second trenches, a gate insulating film formed on a surface of each of the first and second semiconductor layers between the sidewall spacer structures, first and second gate electrodes formed in the first and second trenches respectively on the gate insulating film, first conductivity type impurity regions formed in the first semiconductor layer on both sides of the first gate electrodes, and second conductivity type impurType: ApplicationFiled: December 26, 2000Publication date: November 8, 2001Applicant: Hyundai Electronics Industries Co., Ltd.Inventor: Sang Yeon Kim
-
Publication number: 20010007478Abstract: An apparatus and method for eliminating noise of a received image and compensating its sharpness is provided. A common circuit is used in a structure for eliminating noise based on a double smoothing method and a structure for making the outline sharp based on an unsharp masking method. Noise elimination and sharpness enhancement are processed for a difference signal between an original signal of the image and its low pass filtered signal, thereby compensating the original signal. Thus, an image having an improved picture quality can be provided in a product which transmits/receives or displays image data, and high competitiveness of the product can be obtained by simplifying the user interface.Type: ApplicationFiled: January 12, 2001Publication date: July 12, 2001Applicant: LG Electronics, Inc.Inventor: Sang Yeon Kim
-
Patent number: 6204100Abstract: A CMOS device and a method for fabricating the same, is disclosed, the device including an insulating film formed on a substrate, first and second sapphire patterns formed on the insulating film at fixed intervals, first and second epitaxial semiconductor layers formed on the first and second sapphire patterns, isolating structures formed at edges of the first and second semiconductor layers, respectively, first and second trenches formed down to predetermined depths from surfaces of the first and second semiconductor layers, sidewall spacer structures formed at both sides of the first and second trenches, a gate insulating film formed on a surface of each of the first and second semiconductor layers between the sidewall spacer structures, first and second gate electrodes formed in the first and second trenches respectively on the gate insulating film, first conductivity type impurity regions formed in the first semiconductor layer on both sides of the first gate electrodes, and second conductivity type impurType: GrantFiled: February 12, 1999Date of Patent: March 20, 2001Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Sang Yeon Kim