Abstract: The adjustable lock-in circuits basically include a sensor, a reference voltage, two stacked PMOS transistors, two stacked NMOS transistors, and a feedback line. The sensor compares a feedback voltage with a reference voltage. If the sensing voltage does not reach the reference voltage, the output voltage of the sensor turns on the corresponding transistor, which provides a current to its output until the voltage at feedback reaches the reference voltage. The time to reach the expected voltage level is simply equal to the charge stored at the filter divided by the current, which can be scaled by a device aspect ratio of the transistor. Consequently, all adjustable lock-in circuits provide an adjustable initial loop condition closer to the expected loop condition according to a targeted lock-in time. In addition, the initial loop condition is varied by changing the reference voltage level.

Abstract: One of the high-performance charge-pump circuits basically includes two switch mirror circuits, two current sources, two switches, and an inverter. In the switch mirror, the switch coupled to the diode-connected reference transistor is indirectly mirrored to the output. The great advantage is to utilize the switch mirrors as a part of building cascodes at the output. Consequently, all high-performance charge-pump circuits suppress any charge-injection errors, reduce charge-pump offset, increase the output impedance for effective current injection, and reduce chare-sharing problem.

Abstract: The adjustable start-up circuits basically include a sensor, a reference voltage, two stacked PMOS transistors, two stacked NMOS transistors, and a feedback line. The sensor compares a feedback voltage with a reference voltage. If the sensing voltage does not reach the reference voltage, the output voltage of the sensor turns on the corresponding transistor, which provides a current to its output until the voltage at feedback reaches the reference voltage. The time to reach the expected output voltage level at a load is simply equal to the charge stored at the load divided by the current, which can be scaled by a device aspect ratio of the transistor. Consequently, all adjustable start-up circuits provide an adjustable initial output voltage level closer to the output voltage level that reaches the equilibrium according to schedule. In addition, the output voltage level is varied by changing the reference voltage level.

Abstract: The smart lock-in circuits basically include a sensor, two stacked PMOS transistors, two stacked NMOS transistors, and a feedback line. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensor, the output voltage of the sensor turns on the corresponding transistor, which provides a current to its output until the voltage at feedback reaches the midpoint voltage. The time to reach the midpoint voltage at a filter is simply equal to the charge stored at the filter divided by the current, which can be scaled by a device aspect ratio of the transistor. Consequently, all smart lock-in circuits provide an initial loop condition closer to the expected loop condition according to schedule.

Abstract: The smart start-up circuits basically include a sensor, two stacked PMOS transistors, two stacked NMOS transistors, and a feedback line. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensor, the output voltage of the sensor turns on the corresponding transistor, which provides a current to its output until the voltage at feedback reaches the midpoint voltage. The time to reach the midpoint voltage at a load is simply equal to the charge stored at the load divided by the current, which can be scaled by a device aspect ratio of the transistor. Consequently, all variable start-up circuits provide an initial output voltage level closer to the output voltage level that reaches the equilibrium according to schedule.

Abstract: The variable lock-in circuits basically include a sensor, triggering transistors, current mirror, current source, an N-bit triggering circuit array, and a feedback line. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensor, the output voltage of the sensor turns on the triggering transistors, which provide a total current to its output through the current mirror until the voltage at feedback reaches the midpoint voltage. The time to reach the midpoint voltage at a filter is simply equal to the charge stored at the filter divided by the total current, which is controlled by an N-bit digital input and a device aspect ratio of each triggering transistor. Consequently, all variable lock-in circuits provide an initial loop condition closer to the expected loop condition according to schedule.

Abstract: The variable start-up circuits basically include a sensor, triggering transistors, current mirror, current source, an N-bit triggering circuit array, and a feedback line. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensor, the output voltage of the sensor turns on the triggering transistors, which provide a total current to its output through the current mirror until the voltage at feedback reaches the midpoint voltage. The time to reach the midpoint voltage at a load is simply equal to the charge stored at the load divided by the total current, which is controlled by an N-bit digital input and a device aspect ratio of each triggering transistor. Consequently, all variable start-up circuits provide an output voltage level closer to the output voltage level that reaches the equilibrium according to schedule.

Abstract: The four types of the Z-state circuits basically include a sensing gate, two stacked PMOS transistors, and a feedback line. The sensing gate senses a voltage at its input assuming no feedback is applied. Again, the corresponding output of two stacked PMOS transistors is assumed to be connected to the sensing input. Two stacked PMOS transistors generate a high impedance Z-state at its output according to the corresponding gate voltages. Therefore, the feedback line keeps sampling the output and feeding back the output voltage to the sensing input. Consequently, the feedback configuration provides the initial output voltage, which is the midpoint voltage decided by the device aspect ratios of the sensing gate before normal operation starts.

Abstract: The four types of the Z-state circuits basically include a sensing gate, two stacked PMOS transistors, and a feedback line. The sensing gate senses a voltage at its input assuming no feedback is applied. Again, the corresponding output of two stacked PMOS transistors is assumed to be connected to the sensing input. Two stacked PMOS transistors generate a high impedance Z-state at its output according to the corresponding gate voltages. Therefore, the feedback line keeps sampling the output and feeding back the output voltage to the sensing input. Consequently, the feedback configuration provides the initial loop condition, which is affected by the midpoint voltage decided by the device aspect ratios of the sensing gate before normal operation starts.

Abstract: The four types of the Z-state circuits basically include a sensing gate, two stacked PMOS transistors, and a feedback line. The sensing gate senses a voltage at its input assuming no feedback is applied. Again, the corresponding output of two stacked PMOS transistors is assumed to be connected to the sensing input. Two stacked PMOS transistors generate a high impedance Z-state at its output according to the corresponding gate voltages. Therefore, the feedback line keeps sampling the output and feeding back the output voltage to the sensing input. Consequently, the feedback configuration provides the initial loop condition, which is affected by the midpoint voltage decided by the device aspect ratios of the sensing gate before normal operation starts.

Abstract: The four types of the controllable idle time current mirror circuits are presented with an improvement in productivity, performance, cost, chip area, power consumption, and design time. The controllable idle time current mirror circuits basically include a sensing block, triggering transistors, current mirror, current source, a n-bit control circuit array, and a feedback line. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensing gate, the triggering transistors provide a current to its output through the current mirror until the voltage at feedback reaches the midpoint voltage. Time to reach the midpoint voltage at a load is simply equal to the charge stored at the load divided by the total current, which is controlled by an N-bit digital input and a device aspect ratio of each triggering transistor.

Abstract: The four types of the zero idle time Z-state circuits are presented with an improvement in productivity, cost, chip area, power consumption, and design time. The zero idle time Z-state circuits basically include a sensing gate, two stacked PMOS transistors, and a feedback line. The sensing gate senses a voltage at its input assuming no feedback is applied. Again, the corresponding output of two stacked PMOS transistors is assumed to be connected to the sensing input. Two stacked PMOS transistors generate a high impedance Z-state at its output according to the corresponding output of the sensing gate. Therefore, the feedback line keeps sampling the output and feeding back the output voltage to the sensing input. Consequently, the feedback configuration provides the initial output voltage, which is the midpoint voltage decided by the device aspect ratios of the sensing gate before normal operation starts in all three systems such as all kinds of phase-locked loops, delay-locked loops, and switching regulators.

Abstract: The four types of the Z-state circuits basically include a sensing gate, two stacked PMOS transistors, and a feedback line. The sensing gate senses a voltage at its input assuming no feedback is applied. Again, the corresponding output of two stacked PMOS transistors is assumed to be connected to the sensing input. Two stacked PMOS transistors generate a high impedance Z-state at its output according to the corresponding gate voltages. Therefore, the feedback line keeps sampling the output and feeding back the output voltage to the sensing input. Consequently, the feedback configuration provides the initial output voltage, which is the midpoint voltage decided by the device aspect ratios of the sensing gate before normal operation starts.

Abstract: The n-bit A/D converter of the present invention includes a resistor network, n comparators, and (2.sup.n -1-n) multiplexers. The resistor network generates a plurality of reference voltages characterized by uniform voltage increments between two fixed voltages. The n comparators are coupled to the resistor network. Each comparator receives a reference voltage and an analog input signal. Based on these inputs, an ith comparator generates an ith bit output in the n-bit digital signal where i ranges from 1 to n with the first bit being the most-significant-bit and the nth bit being the least-significant-bit. The (2.sup.n -1-n) multiplexers are coupled between the resistor network and the ith comparator. In response to the output of comparators (except for the first comparator) associated with the more significant bits, the (2.sup.i-1 -1) multiplexers select a reference voltage and transmit it to the ith comparator.