Patents by Inventor Sang-Don Nam
Sang-Don Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9224593Abstract: The inventive concept provides porous, low-k dielectric materials and methods of manufacturing and using the same. In some embodiments, porous, low-k dielectric materials are manufactured by forming a porogen-containing dielectric layer on a substrate and then removing at least a portion of said porogen from the layer.Type: GrantFiled: September 23, 2011Date of Patent: December 29, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Hoon Ahn, Kyu-Hee Han, Kyoung-Hee Kim, Gil-Heyun Choi, Byung-Hee Kim, Sang-Don Nam
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Patent number: 8569862Abstract: A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer.Type: GrantFiled: March 11, 2013Date of Patent: October 29, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Hoon Ahn, Gil-Heyun Choi, Jong-Myeong Lee, Sang-Don Nam, Kyu-Hee Han
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Patent number: 8524615Abstract: Example embodiments relate to a method of forming a hardened porous dielectric layer. The method may include forming a dielectric layer containing porogens on a substrate, transforming the dielectric layer into a porous dielectric layer using a first UV curing process to remove the porogens from the dielectric layer, and transforming the porous dielectric layer into a crosslinked porous dielectric layer using a second UV curing process to generate crosslinks in the porous dielectric layer.Type: GrantFiled: September 21, 2011Date of Patent: September 3, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Hoon Ahn, Byung-Hee Kim, Sang-Don Nam, Kyu-Hee Han, Gil-heyun Choi, Jang-Hee Lee, Jong-Min Baek, Kyoung-Hee Kim
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Patent number: 8404579Abstract: A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer.Type: GrantFiled: December 3, 2010Date of Patent: March 26, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Hoon Ahn, Gil-Heyun Choi, Jong-Myeong Lee, Sang-Don Nam, Kyu-Hee Han
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Patent number: 8298910Abstract: Provided is a method for fabricating a semiconductor device, including forming an interconnect structure including first and second interconnects and an insulating material between the first and second interconnects, forming a first mask layer and a second mask layer having a plurality of micropores sequentially on the interconnect structure, coalescing the plurality of micropores in the second mask layer with each other and forming a plurality of first microholes in the second mask layer, forming a plurality of second microholes in the first mask layer using the plurality of first microholes, and removing the insulating material using the first mask layer with the plurality of second microholes as an etch mask so as to form an air-gap between the first and second interconnects.Type: GrantFiled: March 26, 2010Date of Patent: October 30, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Don Nam, Sang-Hoon Ahn, Eunkee Hong
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Publication number: 20120178253Abstract: The inventive concept provides porous, low-k dielectric materials and methods of manufacturing and using the same. In some embodiments, porous, low-k dielectric materials are manufactured by forming a porogen-containing dielectric layer on a substrate and then removing at least a portion of said porogen from the layer.Type: ApplicationFiled: September 23, 2011Publication date: July 12, 2012Inventors: Sang-Hoon Ahn, Kyu-Hee Han, Kyoung-Hee Kim, Gil-Heyun Choi, Byung-Hee Kim, Sang-Don Nam
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Publication number: 20120083117Abstract: Example embodiments relate to a method of forming a hardened porous dielectric layer. The method may include forming a dielectric layer containing porogens on a substrate, transforming the dielectric layer into a porous dielectric layer using a first UV curing process to remove the porogens from the dielectric layer, and transforming the porous dielectric layer into a crosslinked porous dielectric layer using a second UV curing process to generate crosslinks in the porous dielectric layer.Type: ApplicationFiled: September 21, 2011Publication date: April 5, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Hoon Ahn, Byung-Hee Kim, Sang-Don Nam, Kyu-Hee Han, Gil-Heyun Choi, Jang-Hee Lee, Jong-Min Baek, Kyoung-Hee Kim
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Publication number: 20110263117Abstract: A method of manufacturing a semiconductor device and an apparatus for manufacturing a semiconductor device in which moisture is removed from a porous low-dielectric layer after a chemical mechanical polishing (CMP) process include formation of a porous low-dielectric layer on a substrate. A metal interconnection is formed on the substrate having the porous low-dielectric layer. The metal interconnection forms a planar surface with the porous low-dielectric layer to fill the openings. Ultraviolet (UV) light is irradiated to the porous low-dielectric layer to remove absorbed moisture from the porous low-dielectric layer. A capping layer is formed on the substrate having the porous low-dielectric layer and the metal interconnection. The capping layer is formed in-situ to prevent additional absorption of moisture.Type: ApplicationFiled: April 26, 2011Publication date: October 27, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Don Nam, Sang-Hoon Ahn, Byung-Hee Kim, Kyu-Hee Han
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Patent number: 8026543Abstract: A phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation. In one embodiment, a semiconductor memory device includes a molding layer disposed over semiconductor substrate, a phase-changeable material pattern, and an oxidation barrier of electrically insulative material. The molding layer has a protrusion at its upper portion. One portion of the phase-changeable material pattern overlies the protrusion of the molding layer, and another portion of the phase-changeable material pattern extends through the protrusion. The electrically insulative material of the oxidation barrier may cover the phase-changeable material pattern and/or extend along and cover the entire area at which the protrusion of the molding layer and the portion of the phase-change material pattern disposed on the protrusion adjoin.Type: GrantFiled: December 18, 2008Date of Patent: September 27, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Yoon-Jong Song, Young-Nam Hwang, Sang-Don Nam, Sung-Lae Cho, Gwan-Hyeob Koh, Choong-Man Lee, Bong-Jin Kuh, Yong-Ho Ha, Su-Youn Lee, Chang-Wook Jeong, Ji-Hye Yi, Kyung-Chang Ryoo, Se-Ho Lee, Su-Jin Ahn, Soon-Oh Park, Jang-Eun Lee
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Publication number: 20110136332Abstract: A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer.Type: ApplicationFiled: December 3, 2010Publication date: June 9, 2011Inventors: Sang-Hoon Ahn, Gil-Heyun Choi, Jong-Myeong Lee, Sang-Don Nam, Kyu-Hee Han
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Publication number: 20110071302Abstract: The present invention relates a novel method of preparing an intermediate which is useful for synthesizing an antiulcerant. The present invention provides a method of preparing an intermediate of an antiulcerant which can obtain a high purity compound in high yield, with reduced production cost/time as compared to a conventional method.Type: ApplicationFiled: November 20, 2008Publication date: March 24, 2011Applicant: IL-YANG PHARM. CO., LTD.Inventors: Dong Yeon Kim, Jun Yeoun Lee, Kwi Hyung Cho, Sung Tae Park, Jung Woo Kim, Doo Hyuk Pyun, Sang Don Nam, Hee Yun Kim
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Publication number: 20100248471Abstract: Provided is a method for fabricating a semiconductor device, including forming an interconnect structure including first and second interconnects and an insulating material between the first and second interconnects, forming a first mask layer and a second mask layer having a plurality of micropores sequentially on the interconnect structure, coalescing the plurality of micropores in the second mask layer with each other and forming a plurality of first microholes in the second mask layer, forming a plurality of second microholes in the first mask layer using the plurality of first microholes, and removing the insulating material using the first mask layer with the plurality of second microholes as an etch mask so as to form an air-gap between the first and second interconnects.Type: ApplicationFiled: March 26, 2010Publication date: September 30, 2010Inventors: Sang-Don Nam, Sang-Hoon Ahn, Eunkee Hong
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Patent number: 7622379Abstract: Methods of forming a metal contact structure include forming an interlayer insulating layer on a substrate, etching the interlayer insulating layer to form a hole, depositing a metal layer on the surface of the interlayer insulating layer including inside the hole, planarizing the metal layer to provide a buried portion of the metal layer in the hole and to remove portions of the metal layer outside of the hole, etching-back the buried portion of the metal layer in the hole such that some of the portion of the metal layer within the hole remains and depositing a conductive layer on the surface of the interlayer insulating layer and the portion of the metal layer that remains within the hole. Methods of forming a phase change memory device are also provided.Type: GrantFiled: March 18, 2005Date of Patent: November 24, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Suk-Hun Choi, Byeong-ok Cho, Yoon-ho Son, Sang-don Nam
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Patent number: 7560760Abstract: A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of row and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes.Type: GrantFiled: September 24, 2007Date of Patent: July 14, 2009Assignee: Samung Electronics Co., Ltd.Inventors: Hyun-Ho Kim, Dong-Jin Jung, Ki-Nam Kim, Sang-Don Nam, Kyu-Mann Lee
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Publication number: 20090101881Abstract: In one embodiment, a phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation and a method of manufacturing the same. In one embodiment, a semiconductor memory device comprises a molding layer overlying a semiconductor substrate. The molding layer has a protrusion portion vertically extending from a top surface thereof. The device further includes a phase-changeable material pattern adjacent the protrusion portion and a lower electrode electrically connected to the phase-changeable material pattern.Type: ApplicationFiled: December 18, 2008Publication date: April 23, 2009Applicant: Samsung Electronics Co., Ltd.Inventors: Yoon-Jong Song, Young-Nam Hwang, Sang-Don Nam, Sung-Lae Cho, Gwan-Hyeob Koh, Choong-Man Lee, Bong-Jin Kuh, Yong-Ho Ha, Su-Youn Lee, Chang-Wook Jeong, Ji-Hye Yi, Kyung-Chang Ryoo, Se-Ho Lee, Su-Jin Ahn, Soon-Oh Park, Jang-Eun Lee
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Patent number: 7517703Abstract: A ferroelectric memory device and a method of forming the same are provided. At least two lower electrode patterns are formed on an interlayer insulating layer covering a semiconductor substrate. A seed layer pattern filling a space between at least the two lower electrode patterns and having a planar surface is formed. A ferroelectric layer is formed on the lower electrode pattern and the seed layer pattern. An upper electrode overlapping the two lower electrode patterns is formed on the ferroelectric layer.Type: GrantFiled: June 15, 2007Date of Patent: April 14, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Yoon-Ho Son, Sang-Don Nam, Suk-Hun Choi
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Patent number: 7482616Abstract: In one embodiment, a phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation and a method of manufacturing the same. In one embodiment, a semiconductor memory device comprises a molding layer overlying a semiconductor substrate. The molding layer has a protrusion portion vertically extending from a top surface thereof. The device further includes a phase-changeable material pattern adjacent the protrusion portion and a lower electrode electrically connected to the phase-changeable material pattern.Type: GrantFiled: May 27, 2005Date of Patent: January 27, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Yoon-Jong Song, Young-Nam Hwang, Sang-Don Nam, Sung-Lae Cho, Gwan-Hyeob Koh, Choong-Man Lee, Bong-Jin Kuh, Yong-Ho Ha, Su-Youn Lee, Chang-Wook Jeong, Ji-Hye Yi, Kyung-Chang Ryoo, Se-Ho Lee, Su-Jin Ahn, Soon-Oh Park, Jang-Eun Lee
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Publication number: 20080025065Abstract: A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of row and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes.Type: ApplicationFiled: September 24, 2007Publication date: January 31, 2008Inventors: Hyun-Ho Kim, Dong-Jin Jung, Ki-Nam Kim, Sang-Don Nam, Kyu-Mann Lee
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Patent number: 7285810Abstract: A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of rows and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes.Type: GrantFiled: September 23, 2004Date of Patent: October 23, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Ho Kim, Dong-Jin Jung, Ki-Nam Kim, Sang-Don Nam, Kyu-Mann Lee
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Publication number: 20070243641Abstract: A ferroelectric memory device and a method of forming the same are provided. At least two lower electrode patterns are formed on an interlayer insulating layer covering a semiconductor substrate. A seed layer pattern filling a space between at least the two lower electrode patterns and having a planar surface is formed. A ferroelectric layer is formed on the lower electrode pattern and the seed layer pattern. An upper electrode overlapping the two lower electrode patterns is formed on the ferroelectric layer.Type: ApplicationFiled: June 15, 2007Publication date: October 18, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoon-Ho Son, Sang-Don Nam, Suk-Hun Choi