Patents by Inventor Sanghoon Bae

Sanghoon Bae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170062780
    Abstract: A battery module, including a plurality of battery units each including a plurality of bare cells, each bare cell having a first electrode tab and a second electrode tab; a holder at one side of each of the battery units, the holder including a plurality of penetrating holes into each of which the first electrode tab and the second electrode tab are penetrated; a plurality of electrode plates in the holder, the plurality of electrode plates electrically connecting the bare cells in each of the battery units; connection members coupled to ends of one of the plurality of electrode plates, the connection members electrically connecting the plurality of battery units to each other, and a pair of mounting protrusions protruding from one side of the holder and being spaced apart from each other, a portion of one of the plurality of electrode plates passing between the pair of mounting protrusions.
    Type: Application
    Filed: August 24, 2016
    Publication date: March 2, 2017
    Inventor: Sanghoon BAE
  • Publication number: 20160322617
    Abstract: A battery pack, including a battery cell; a case providing an accommodation space in which the battery cell is disposed; inert gas filled in the accommodation space; and a gas inlet/outlet portion in the case, the gas inlet/outlet portion in contact with the accommodation space, the gas inlet/outlet portion being for injecting gas into the accommodation space and discharging gas from the accommodation space.
    Type: Application
    Filed: January 5, 2016
    Publication date: November 3, 2016
    Inventors: Sanghoon BAE, Somin KIM
  • Patent number: 9323393
    Abstract: Various techniques and apparatuses are disclosed that provide for pixelated display modules that integrate an ultrasonic fingerprint or biometric sensing capability. In some implementations, the ultrasonic fingerprint sensor and the display components of the display module may share a common backplane. In some implementations, the ultrasonic fingerprint sensor may share a flex cable with other components in the display module. In some implementations, the ultrasonic fingerprint sensor may leverage conductive traces on a cover glass used to provide for touch input to the display module.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: April 26, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Kostadin Dimitrov Djordjev, Leonard Eugene Fennell, Nicholas Ian Buchan, David William Burns, Samir K. Gupta, Sanghoon Bae
  • Publication number: 20160073046
    Abstract: A pixel sensor array includes a plurality of pixel sensors having a first gain and a plurality of pixel sensors having a second gain less than the first gain.
    Type: Application
    Filed: November 16, 2015
    Publication date: March 10, 2016
    Inventors: Rastislav Lukac, Shri Ramaswami, Sanghoon Bae
  • Patent number: 9191556
    Abstract: A pixel sensor array includes a plurality of pixel sensors having a first gain and a plurality of pixel sensors having a second gain less than the first gain.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: November 17, 2015
    Assignee: Foveon, Inc.
    Inventors: Rastislav Lukac, Shri Ramaswami, Sanghoon Bae
  • Publication number: 20140354596
    Abstract: Various techniques and apparatuses are disclosed that provide for pixelated display modules that integrate an ultrasonic fingerprint or biometric sensing capability. In some implementations, the ultrasonic fingerprint sensor and the display components of the display module may share a common backplane. In some implementations, the ultrasonic fingerprint sensor may share a flex cable with other components in the display module. In some implementations, the ultrasonic fingerprint sensor may leverage conductive traces on a cover glass used to provide for touch input to the display module.
    Type: Application
    Filed: November 4, 2013
    Publication date: December 4, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Kostadin Dimitrov Djordjev, Leonard Eugene Fennell, Nicholas Ian Buchan, David William Burns, Samir K. Gupta, Sanghoon Bae
  • Publication number: 20140212737
    Abstract: A battery pack includes a spacer. The spacer for the battery pack can be used by being cut according to the number of batteries received in the battery pack, and can thus be applied to multiple battery packs in which different numbers of batteries are received, and can be easily separated manually. In one type of spacer, a first plurality of concave battery receiving parts corresponding to portions of outer surfaces of the cylindrical batteries are formed on a first surface of a rectangular frame, and cutting grooves are formed in the respective battery receiving parts in a direction corresponding to the center axes of the cylindrical batteries to facilitate cutting of the spacer.
    Type: Application
    Filed: July 29, 2013
    Publication date: July 31, 2014
    Applicant: Samsung SDI Co., Ltd.
    Inventors: Sanghoon Bae, Youngbin Ko
  • Publication number: 20130027591
    Abstract: A pixel sensor array includes a plurality of pixel sensors having a first gain and a plurality of pixel sensors having a second gain less than the first gain.
    Type: Application
    Filed: July 16, 2012
    Publication date: January 31, 2013
    Inventors: Rastislav Lukac, Shri Ramaswami, Sanghoon Bae
  • Patent number: 7427526
    Abstract: This invention uses large surface to volume ratio materials for separation, release layer, and sacrificial material applications. The invention outlines the material concept, application designs, and fabrication methodologies. The invention is demonstrated using deposited column/void network materials as examples of large surface to volume ratio materials. In a number of the specific applications discussed, it is shown that it is advantageous to create structures on a laminate on a mother substrate and then, using the separation layer material approach, to separate this laminate from the mother substrate using the present separation scheme. It is also shown that the present materials have excellent release layer utility. In a number of applications it is also shown how the approach can be used to uniquely form cavities, channels, air-gaps, and related structures in or on various substrates.
    Type: Grant
    Filed: April 17, 2001
    Date of Patent: September 23, 2008
    Assignee: The Penn State Research Foundation
    Inventors: Stephen J. Fonash, Wook Jun Nam, Youngchul Lee, Kyuhwan Chang, Daniel J. Hayes, A. Kaan Kalkan, Sanghoon Bae
  • Patent number: 6794196
    Abstract: The present invention is directed to the use of deposited thin films for chemical or biological analysis. The invention further relates to the use of these thin films in separation adherence and detection of chemical of biological samples. Applications of these thin films include desorption-ionization mass spectroscopy, electrical contacts for organic thin films and molecules, optical coupling of light energy for analysis, biological materials manipulation, chromatographic separation, head space adsorbance media, media for atomic molecular adsorbance or attachment, and substrates for cell attachment.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: September 21, 2004
    Assignee: The Penn State Research Foundation
    Inventors: Stephen J. Fonash, Sanghoon Bae, Daniel J. Hayes, Joseph Cuiffi
  • Publication number: 20020132101
    Abstract: A novel porous film is disclosed comprising a network of silicon columns in a continuous void which may be fabricated using high density plasma deposition at low temperatures, i.e., less than about 250 ° C. This silicon film is a two-dimensional nano-sized array of rodlike columns. This void-column morphology can be controlled with deposition conditions and the porosity can be varied up to 90%. The simultaneous use of low temperature deposition and etching in the plasma approach utilized, allows for the unique opportunity of obtaining columnar structure, a continuous void, and polycrystalline column composition at the same time. Unique devices may be fabricated using this porous continuous film by plasma deposition of this film on a glass, metal foil, insulator or plastic substrates.
    Type: Application
    Filed: March 22, 2002
    Publication date: September 19, 2002
    Applicant: The Penn State Research Foundation
    Inventors: Stephen J. Fonash, Alikaan Kalkan, Sanghoon Bae
  • Patent number: 6399177
    Abstract: A novel porous film is disclosed comprising a network of silicon columns in a continuous void which may be fabricated using high density plasma deposition at low temperatures, i.e., less than about 250° C. This silicon film is a two-dimensional nano-sized array of rodlike columns. This void-column morphology can be controlled with deposition conditions and the porosity can be varied up to 90%. The simultaneous use of low temperature deposition and etching in the plasma approach utilized, allows for the unique opportunity of obtaining columnar structure, a continuous void, and polycrystalline column composition at the same time. Unique devices may be fabricated using this porous continuous film by plasma deposition of this film on a glass, metal foil, insulator or plastic substrates.
    Type: Grant
    Filed: May 30, 2000
    Date of Patent: June 4, 2002
    Assignee: The Penn State Research Foundation
    Inventors: Stephen J. Fonash, Ali Kaan Kalkan, Sanghoon Bae
  • Publication number: 20020048531
    Abstract: The present invention is directed to the use of deposited thin films for chemical or biological analysis. The invention further relates to the use of these thin films in separation adherence and detection of chemical of biological samples. Applications of these thin films include desorption-ionization mass spectroscopy, electrical contacts for organic thin films and molecules, optical coupling of light energy for analysis, biological materials manipulation, chromatographic separation, head space adsorbance media, media for atomic molecular adsorbance or attachment, and substrates for cell attachment.
    Type: Application
    Filed: December 19, 2000
    Publication date: April 25, 2002
    Inventors: Stephen J. Fonash, Sanghoon Bae, Daniel J. Hayes, Joseph Cuiffi
  • Publication number: 20020020053
    Abstract: This invention uses large surface to volume ratio materials for separation, release layer, and sacrificial material applications. The invention outlines the material concept, application designs, and fabrication methodologies. The invention is demonstrated using deposited column/void network materials as examples of large surface to volume ratio materials. In a number of the specific applications discussed, it is shown that it is advantageous to create structures on a laminate on a mother substrate and then, using the separation layer material approach, to separate this laminate from the mother substrate using the present separation scheme. It is also shown that the present materials have excellent release layer utility. In a number of applications it is also shown how the approach can be used to uniquely form cavities, channels, air-gaps, and related structures in or on various substrates.
    Type: Application
    Filed: April 17, 2001
    Publication date: February 21, 2002
    Inventors: Stephen J. Fonash, Wook Jun Nam, Youngchul Lee, Kyuhwan Chang, Daniel J. Hayes, A. Kaan Kalkan, Sanghoon Bae
  • Patent number: 6277714
    Abstract: The method of the invention induces crystallization in an amorphous semiconductor layer, and includes the steps of: a) producing a patterned metal layer on a first substrate, the metal layer exhibiting a weak level of adherence to the first substrate; b) pressing the metal layer into physical contact with the amorphous semiconductor layer; c) applying heat, light or both to the metal layer and amorphous semiconductor layer to cause a reaction therebetween and a crystallization of the amorphous semiconductor that is juxtaposed to the metal.
    Type: Grant
    Filed: September 21, 1999
    Date of Patent: August 21, 2001
    Assignee: The Penn State Research Foundation
    Inventors: Stephan J. Fonash, Sanghoon Bae