Patents by Inventor Sang-woong Shin

Sang-woong Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240322727
    Abstract: A motor-driving apparatus for driving a motor having a plurality of windings respectively corresponding to a plurality of phases is provided. The motor-driving apparatus includes a first inverter having a plurality of first switching devices and connected to first ends of the plurality of windings and a second inverter having a plurality of second switching devices and connected to second ends of the plurality of windings. A third switching device is configured to selectively connect and disconnect points at which a number of turns of each of the windings is divided in a preset ratio. A controller is configured to adjust an on/off state of the first to third switching devices based on required output of the motor.
    Type: Application
    Filed: June 7, 2024
    Publication date: September 26, 2024
    Inventors: Kang Ho Jeong, Jong Kyong Lim, Suk Hyun Lim, Ji Woong Jang, Beom Sik Kim, Sang Cheol Shin
  • Publication number: 20240279203
    Abstract: The present invention relates to novel mesylate salt of N-(5-(4-(4-((dimethylamino)methyl)-3-phenyl-1H-pyrazol-1-yl)pyrimidine-2-ylamino)-4-methoxy-2-morpholinophenyl)acrylamide, a novel crystalline form thereof, and a process for preparing the same. More specifically, the present invention relates to mesylate salt of N-(5-(4-(4-((dimethylamino)methyl)-3-phenyl-1H-pyrazol-1-yl)pyrimidine-2-ylamino)-4-methoxy-2-morpholinophenyl)acrylamide, which is excellent in stability, solubility, and bioavailability when it is administered not only alone but also in combination with other drugs and which has a high purity, a crystalline form thereof, and a process for preparing the same.
    Type: Application
    Filed: March 27, 2024
    Publication date: August 22, 2024
    Inventors: Sang Ho OH, Jong Gyun KIM, Se-Woong OH, Tae Dong HAN, Soo Yong CHUNG, Seong Ran LEE, Kyeong Bae KIM, Young Sung LEE, Woo Seob SHIN, Hyun JU, Jeong Ki KANG, Su Min PARK, Dong Kyun KIM
  • Patent number: 8873277
    Abstract: A semiconductor memory device includes a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: October 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-won Seo, Soo-ho Shin, Won-woo Lee, Jeong-soo Park, Young-yong Byun, Seong-jin Jang, Sang-woong Shin
  • Patent number: 8514610
    Abstract: A semiconductor memory cell array includes a plurality of bit-lines, a plurality of word-lines, a plurality of memory cells, a plurality of dummy memory cells, a plurality of dummy bit-lines, and a plurality of dummy word-lines. The dummy bit-lines are in outer regions of the bit-lines. The dummy word-lines are in outer regions of the word-lines. The dummy bit-lines are maintained in a floating state. The dummy word-lines retain a turn-off voltage.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 20, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Woong Shin, Seong-Jin Jang
  • Publication number: 20130094320
    Abstract: Address transforming methods are provided. The methods may include generating a power-up signal when a semiconductor memory device is powered-up. The methods may further include generating a randomized output signal in response to the power-up signal. The methods may additionally include transforming bits of a first address in response to the randomized output signal to generate a second address.
    Type: Application
    Filed: September 12, 2012
    Publication date: April 18, 2013
    Inventors: Jae-Ki YOO, Sang-Hyuk Kwon, Sang-Woong Shin, In-Chul Jeong
  • Patent number: 8374043
    Abstract: A sense amplifier having a pre-amplifier and a main-amplifier is disclosed. The pre-amplifier is connected to paired data line, senses and amplifies data on the paired data line using voltage mode and outputting a pair of differential signal. The main-amplifier is connected to the paired data line, senses and amplifies data on the paired data line using current mode and generating a first amplified signal, senses and amplifies the first amplified signal using voltage mode in response to the pair of differential signal, and outputting an amplified data.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: February 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Bae Lee, Sang-Woong Shin
  • Publication number: 20130003479
    Abstract: A semiconductor memory cell array includes a plurality of bit-lines, a plurality of word-lines, a plurality of memory cells, a plurality of dummy memory cells, a plurality of dummy bit-lines, and a plurality of dummy word-lines. The dummy bit-lines are in outer regions of the bit-lines. The dummy word-lines are in outer regions of the word-lines. The dummy bit-lines are maintained in a floating state.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 3, 2013
    Inventors: Sang-Woong SHIN, Seong-Jin JANG
  • Patent number: 8310859
    Abstract: A semiconductor memory device includes a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: November 13, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-won Seo, Soo-ho Shin, Won-woo Lee, Jeong-soo Park, Young-yong Byun, Seong-jin Jang, Sang-woong Shin
  • Patent number: 8295114
    Abstract: A semiconductor memory cell array includes a plurality of bit-lines, a plurality of word-lines, a plurality of memory cells, a plurality of dummy memory cells, a plurality of dummy bit-lines, and a plurality of dummy word-lines. The dummy bit-lines are in outer regions of the bit-lines. The dummy word-lines are in outer regions of the word-lines. The dummy bit-lines are maintained in a floating state. The dummy word-lines retain a turn-off voltage.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: October 23, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Woong Shin, Seong-Jin Jang
  • Patent number: 8258856
    Abstract: An antifuse circuit includes a protection circuit. The antifuse circuit receives a program voltage using a non-connection (NC) pin or ball of a semiconductor device. The protection circuit prevents an unintended voltage lower than the program voltage from being applied to the antifuse circuit.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: September 4, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Cheon-An Lee, Seong-Jin Jang, Sang-Woong Shin
  • Publication number: 20110069568
    Abstract: A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current.
    Type: Application
    Filed: November 23, 2010
    Publication date: March 24, 2011
    Inventors: Sang-Woong Shin, Chul-Soo Kim, Young-Hyun Jun, Sang-Bo Lee
  • Patent number: 7855926
    Abstract: A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: December 21, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Woong Shin, Chul-Soo Kim, Young-Hyun Jun, Sang-Bo Lee
  • Patent number: 7814359
    Abstract: A high-speed double or quadrature data rate interface semiconductor device and a method thereof are provided. A transmitter (e.g., a data transmitting semiconductor device) for high-speed data transmission transmits a first strobe signal and a second strobe signal, which have a phase difference of 90 degrees there-between, a first group (byte of) data, and a second group (byte of) data. The transmitter adjusts the phase of at least one of the first and second strobe signals based on phase-error information fed back from a receiver and then transmits the phase-adjusted strobe signal to the receiver. The receiver receives the first and second strobe signals from the transmitter and receives the first group (byte of) data and the second group (byte of) data using the first and second strobe signals. The receiver does not require a phase-locked loop (PLL) or a delay-locked loop (DLL), thereby decreasing the circuit area and power consumption of the receiver.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: October 12, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Jun Bae, Seong-Jin Jang, Kwang-Il Park, Sang-Woong Shin, Ho-Young Song
  • Publication number: 20100214861
    Abstract: A semiconductor memory cell array includes a plurality of bit-lines, a plurality of word-lines, a plurality of memory cells, a plurality of dummy memory cells, a plurality of dummy bit-lines, and a plurality of dummy word-lines. The dummy bit-lines are in outer regions of the bit-lines. The dummy word-lines are in outer regions of the word-lines. The dummy bit-lines are maintained in a floating state.
    Type: Application
    Filed: February 22, 2010
    Publication date: August 26, 2010
    Inventors: Sang-Woong Shin, Seong-Jin Jang
  • Publication number: 20100134175
    Abstract: An antifuse circuit includes a protection circuit. The antifuse circuit receives a program voltage using a non-connection (NC) pin or ball of a semiconductor device. The protection circuit prevents an unintended voltage lower than the program voltage from being applied to the antifuse circuit.
    Type: Application
    Filed: November 16, 2009
    Publication date: June 3, 2010
    Inventors: Cheon-An Lee, Seong-Jin Jang, Sang-Woong Shin
  • Publication number: 20100128545
    Abstract: A sense amplifier having a pre-amplifier and a main-amplifier is disclosed. The pre-amplifier is connected to paired data line, senses and amplifies data on the paired data line using voltage mode and outputting a pair of differential signal. The main-amplifier is connected to the paired data line, senses and amplifies data on the paired data line using current mode and generating a first amplified signal, senses and amplifies the first amplified signal using voltage mode in response to the pair of differential signal, and outputting an amplified data.
    Type: Application
    Filed: May 1, 2009
    Publication date: May 27, 2010
    Inventors: Hyun-Bae LEE, Sang-Woong SHIN
  • Publication number: 20100080044
    Abstract: According to some of the inventive concepts, a semiconductor memory device may include a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.
    Type: Application
    Filed: September 30, 2009
    Publication date: April 1, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeoung-won SEO, Young-yong BYUN, Seong-jin JANG, Sang-woong SHIN, Soo-ho SHIN, Won-woo LEE, Jeong-soo PARK
  • Patent number: 7587645
    Abstract: An input circuit of a semiconductor memory device includes a data input circuit and a data pattern setting circuit. The data input circuit receives first data, and generates second data by buffering the first data, sampling buffered first data responsive to a write data strobe (WDQS) signal, and parallelizing sampled data. The data pattern setting circuit sets a pattern of the second data responsive to a test mode signal and a data pattern select signal to generate third data. Accordingly, the semiconductor memory device including the input circuit may generate data of various patterns in a test mode, and may perform a high-speed test using a low-speed tester.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: September 8, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Uk Chang, Sang-Woong Shin
  • Patent number: 7577057
    Abstract: A circuit for generating a write data mask signal in a synchronous semiconductor memory device includes an output unit and a reset control unit. The output unit controls a write data mask operation of the synchronous semiconductor memory device, latches a write data mask signal, and outputs an internal write data mask signal, in response to an internal clock signal. The reset control unit generates a reset signal for resetting the internal write data mask signal, in response to a write column disable signal indicating an activation end point of a column selection line signal generated when a write operation including the write data mask operation is performed. While the synchronous semiconductor memory device performs a gapless write data mask operation included in a gapless write operation, the reset signal is deactivated so that the write data mask signal is not reset.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: August 18, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soon-seob Lee, Sang-woong Shin
  • Patent number: 7516384
    Abstract: A test device for a semiconductor memory device includes a clock frequency multiplier, a data input buffer, a test data generator and a data output buffer. The clock frequency multiplier multiplies an external clock signal having a relatively low frequency provided from an external test device to generate an internal clock signal having a relatively high frequency. The data input buffer buffers test pattern data provided in synchronization to the external clock signal to output the buffered test pattern data. The test data generator generates test data that is to be synchronized to the internal clock signal, using the outputted test pattern data based on a first or a second control signal. The data output buffer outputs the generated test data to a memory core of the semiconductor memory device. The test device generates various test data suitable for a memory test at a high operating speed.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: April 7, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Jin Jeong, Sang-Woong Shin