Abstract: A mechanism is provided by which a failure analysis during design of one or more memory arrays used in a system on a chip can take into account an operational voltage use profile over the projected life of the chip. The failure analysis is then used in chip redesign decision-making or modification of the use profile. As a result, memory arrays used in chip design can be more closely matched to the actual use of the chip, rather than being overly-conservatively designed, thereby resulting in physically smaller or more efficient memory arrays and thus smaller chips.

Abstract: A method can include identifying a device design comprising first and second instantiations of a device, identifying a layer of the device design, identifying a first region of the device design for the first instantiation based on the layer of the first instantiation, and a second region of the device design for the second instantiation based on the layer of the second instantiation. identifying a first compare layer of the device design that comprises a plurality of first compare features including a first compared feature within the first region and a second compared feature within the second region, determining a difference between the first compared feature and the second compared feature, and determining if the difference meets a tolerance to determine if the first instantiation matches the second instantiation.

Abstract: A method can include generating a first set of sample values for input variables in accordance with a prescribed set of probability distributions, running a set of simulations on an electronic component based upon the first set of sample values, multiplying the standard deviations of the original distributions by a scaling factor ?, generating a second set of sample values for the input variables based on the probability distributions thus generated, and running a set of simulations on the electronic component based on this second set of sample values. The method can also include the generation of Q-Q plots based on the data from the first and second set of simulations and data from a truly normal distribution or the distribution obeyed by the independently varying input parameters; and the use of these plots for assessment of the robustness and functionality of the electronic component.

Abstract: An SRAM has at least two sets of pass transistors for coupling at least two sets of bit lines to true and complement data nodes of an SRAM cell based on the assertion of at least two word lines. The cell includes two pull up transistors and two pull down transistors coupled to the true and complement data nodes. None of the pass transistors are implemented in an active area that includes a pull up transistor or a pull down transistor of the cell.

Abstract: A method can include identifying a device design comprising first and second instantiations of a device, identifying a layer of the device design, identifying a first region of the device design for the first instantiation based on the layer of the first instantiation, and a second region of the device design for the second instantiation based on the layer of the second instantiation. identifying a first compare layer of the device design that comprises a plurality of first compare features including a first compared feature within the first region and a second compared feature within the second region, determining a difference between the first compared feature and the second compared feature, and determining if the difference meets a tolerance to determine if the first instantiation matches the second instantiation.

Abstract: An SRAM has at least two sets of pass transistors for coupling at least two sets of bit lines to true and complement data nodes of an SRAM cell based on the assertion of at least two word lines. The cell includes two pull up transistors and two pull down transistors coupled to the true and complement data nodes. None of the pass transistors are implemented in an active area that includes a pull up transistor or a pull down transistor of the cell.

Abstract: A dual port static random access memory cell has pull-down transistors, pull-up transistors, and pass transistors. A first active region has a first pull-down transistor coupled to a true data node, a second pull-down transistor coupled to a complementary data node; a first pass transistor coupled to the true data node, and a second pass transistor coupled to the complementary data node. A second active region has the same size and shape as the first active region and has a third pull-down transistor coupled in parallel to the first-pull down transistor, a fourth pull-down transistor coupled in parallel to the second pull-down transistor; a third pass transistor coupled to the true data node, and a fourth pass transistor coupled to the complementary data node. A first pull-up transistor and a second pull-up transistor are located between the first and second active regions.

Abstract: A dual port static random access memory cell has pull-down transistors, pull-up transistors, and pass transistors. A first active region has a first pull-down transistor coupled to a true data node, a second pull-down transistor coupled to a complementary data node; a first pass transistor coupled to the true data node, and a second pass transistor coupled to the complementary data node. A second active region has the same size and shape as the first active region and has a third pull-down transistor coupled in parallel to the first-pull down transistor, a fourth pull-down transistor coupled in parallel to the second pull-down transistor; a third pass transistor coupled to the true data node, and a fourth pass transistor coupled to the complementary data node. A first pull-up transistor and a second pull-up transistor are located between the first and second active regions.