Abstract: A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives transactions from a master device, communicates with a master device as another master device or as a slave device, and queues transactions received from a master device. Since the achievement of coherency is distributed in time and space, the node controller helps to maintain cache coherency. A transaction tag format for a standard bus protocol is expanded to ensure unique transaction tags are maintained throughout the system. A sideband signal is used for intervention and Reruns to preserve transaction tags at the node controller in certain circumstances.

Abstract: A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. Each of the processors may have multiple caches. The address switch connects to each of the node controllers and to each of the memory subsystems, and each of the memory subsystems connects to the address switch and to each of the node controllers. The node controller receives commands from a master device and queues commands received from a master device. The buses between the master devices, the node controllers, the address switch, and the memory subsystems are operable using a variety of bus protocols.

Abstract: A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. Due to pin limitations that may be caused by large buses, e.g. buses that support a high number of data pins, the node controller may be implemented such that the functionality for its address paths and data paths are implemented in physically separate components, chips, or circuitry, such as a node data controller or a node address controller.

Abstract: A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives transactions from a master device, communicates with a master device as another master device or as a slave device, and queues transactions received from a master device. Since the achievement of coherency is distributed in time and space, the node controller helps to maintain cache coherency. The node controller also implements an interrupt arbitration scheme designed to choose among multiple eligible interrupt distribution units without using dedicated sideband signals on the bus.

Abstract: A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. The node controller has a deterministic delay between latching a snooped command broadcast by the address switch and presenting the command to the master devices on the node controller's master device buses.

Abstract: A distributed system structure for a large-way, multi-bus, multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. The system allows for the implementation of a bus protocol that reports the state of a cache line to a master device along with the first beat of data delivery for a cacheable coherent Read. Since the achievement of coherency is distributed in time and space, the issue of data integrity is addressed through a variety of actions.

Abstract: A distributed system structure for a large-way, multi-bus, multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. The system allows for the implementation of a bus protocol that reports the state of a cache line to a master device along with the first beat of data delivery for a cacheable coherent Read. Since the achievement of coherency is distributed in time and space, the issue of data integrity is addressed through a variety of actions.

Abstract: A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives transactions from a master device, communicates with a master device as another master device or as a slave device, and queues transactions received from a master device. Since the achievement of coherency is distributed in time and space, the node controller helps to maintain cache coherency. A transaction tag format for a standard bus protocol is expanded to ensure unique transaction tags are maintained throughout the system. A sideband signal is used for intervention and Reruns to preserve transaction tags at the node controller in certain circumstances.

Abstract: A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based ache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. Since the achievement of coherency is distributed in time and space, the node controller helps to eliminate certain types of snoop collisions by pacing commands selected from its queues in certain circumstances.

Abstract: A method for transferring data between devices in a computer system. In a preferred embodiment, a requesting device broadcasts a request for data. Each of a plurality of devices within the computer system responds to the request and indicates the location of the device and whether the device contains the requested data. The data is then transferred to the requesting device from one of the devices containing the data within the plurality of devices to the requesting device. The device selected to transfer the data to the requesting device has the closest logical proximity to the requesting device which results in a quick transfer of data.

Abstract: A method and apparatus for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. Each of the processors may have multiple caches. The address switch connects to each of the node controllers and to each of the memory subsystems, and each of the memory subsystems connects to the address switch and to each of the node controllers. The node controller receives commands from a master device and queues commands received from a master device. The node controller has a deterministic delay between latching a snooped command broadcast by the address switch and presenting the command to the master devices on the node controller's master device buses.

Abstract: A method and system for bypassing a prefetch data path is provided. Each transaction within a system is tagged, and as transactions are issued for retrieving data, the system has a data prefetch unit for prefetching data from a processor, a memory subsystem, or an I/O agent into a prefetch data buffer. A prefetch data buffer entry is allocated for a data prefetch transaction, and the data prefetch transaction is issued. While the prefetch transaction is pending, a read transaction is received from a transaction requestor. The address for the read transaction is compared with the addresses of the pending data prefetch transactions, and in response to an address match, the prefetch data buffer entry for the matching prefetch transaction is checked to determine whether data has been received for the data prefetch transaction.

Abstract: A distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The address switch connects to each of the node controllers and to each of the memory subsystems, and each of the memory subsystems connects to the address switch and to each of the node controllers. The node controller receives commands from a master device. The buses between the master devices, the node controllers, the address switch, and the memory subsystems are operable using a variety of bus protocols. A response combination block connects to the address switch, to each master device, to each node controller, and to each memory subsystem in order to receive, logically combine/generate, and then transmit command status signals and command response signals associated with commands issued by master devices.

Abstract: An arbitration protocol is provided for determining between a pair of subsystems within a networking system having a plurality of subsystems which subsystem might obtain access to a common hardware resource. The protocol allows the networking system to determine which subsystem becomes the sender and which becomes the receiver. The protocol is based on a point-to-point communication between two peer subsystems . It is based on an asymmetrical quality such that the first or priority subsystem has a zero latency in accessing the switch while the second subsystem must wait at least one clock cycle before obtaining access to the network system after requesting it and after the end of control by the first subsystem.

Abstract: A method and system for reissuing load requests in a multi-stream prefetch engine of a data processing system is provided. A read transaction is received from a transaction requester, and the read transaction has a base address and a prefetch stream identifier. The received read transaction is issued to a prefetch stream associated with a data prefetch buffer identified by the prefetch stream identifier as the prefetch stream is one of a set of prefetch streams, each of which has an associated prefetch buffer. The read transaction is issued to a prefetch stream associated with a data prefetch buffer, and a set of prefetch addresses are generated, each prefetch address in the set of prefetch addresses being proximate to the base address.

Abstract: A method and apparatus for providing a distributed implementation of an interrupt delivery controller in a multi-processor environment while maintaining compliance with the OpenPIC specification. Specifically, an interrupt delivery controller is maintained for each one of the central processing units. Whenever one of the central processing units resets its corresponding interrupt delivery controller, logic is used to select it as the primary interrupt controller. The primary interrupt controller coordinates the resetting of the secondary interrupt controller(s) and interrupt source units so that virtually an unlimited number of interrupt source units can be used in the system.

Abstract: A cache coherence network for transferring coherence messages between processor caches in a multiprocessor data processing system is provided. The network includes a plurality of processor caches associated with a plurality of processors, and a binary logic tree circuit which can separately adapt each branch of the tree from a broadcast configuration during low levels of coherence traffic to a ring configuration during high levels of coherence traffic. A cache snoop-in input receives coherence messages and a snoop-out output outputs, at the most, one coherence message per current cycle of the network timing. A forward signal on a forward output indicates that the associated cache is outputting a message on snoop-out during the current cycle. A cache outputs received messages in a queue on the snoop-out output, after determining any response message based on the received message. The binary logic tree circuit has a plurality of binary nodes connected in a binary tree structure.

Abstract: A method and apparatus for providing a distributed implementation of an interrupt delivery controller in compliance with the OpenPIC specification. Specifically, a virtually unlimited number of interrupt source units can be supported without significant degradation of the system. This is accomplished by using a master reset bit for the interrupt delivery controller and a reset bit for each of the interrupt source units for indicating their respective current status. The master reset bit in combination with the reset bits are used to discard interrupts enroute during the resetting of the interrupt delivery controller. Thus, eliminating the requirement of an acknowledgement from each of the interrupt source units concerning their resetting status before proceeding.

Abstract: A distributed information handling system includes one or more processing units, a memory system including one or more memory modules, one or more routers, one or more terminal devices an N port switch which connects selected processing units to selected memory modules and to the terminal devices through the one or more routers, where device configuration is controlled by a configuration routine running in a primary processing unit, and which configures all configurable devices in the system in a tree structured manner, each device being configured with respect to a nearest neighbor in the tree.

Abstract: An arbitration protocol, preferably known as data-valid extended (DVE) protocol, for determining which one of the two units within a computer system may obtain access to a common bus is described. The DVE protocol is based on a point-to-point communication between two peer units. The DVE protocol is a physical level signalling convention for controlling switch communications on bi-directional address buses and data buses in a boundary-latched synchronous environment. The DVE protocol is asymmetric, yet fair, and is designed to minimize the number of cycles spent (or latency) in accessing the address or data buses and to maximize the number useful cycles (or bandwidth) on the address buses as well as the data buses. The asymmetry of the DVE protocol reduces the number of cycles spent in arbitration to zero for any data transfer size greater than one.