Patents by Inventor Sanjay RAJASEKHAR
Sanjay RAJASEKHAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11190197Abstract: Noise sources in a pipelined ADC circuit can include kT/C sampling noise from a capacitor DAC circuit and residue amplifier sampling noise. The kT/C sampling noise is inversely proportional to the size of the sampling capacitors; the larger sampling capacitors produce less noise. However, larger sampling capacitor can be difficult to drive and physically occupy significant die area. By using the described techniques, the inversely proportional relationship between the sampling noise and the size of the sampling capacitors is no longer true. The size of the sampling capacitors can be greats reduced, which can reduce the die area and reduce the power consumption of the ADC, and the kT/C sampling noise can be canceled using correlated double sampling (CDS) techniques.Type: GrantFiled: February 19, 2019Date of Patent: November 30, 2021Assignee: Analog Devices International Unlimited CompanyInventors: Sanjay Rajasekhar, Roberto Sergio Matteo Maurino
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Patent number: 10931122Abstract: A pre-charge circuit is provided for pre-charging the input node of a capacitive component to which the multiplexer output is fed to a charge level that is close to or approximates the signal output level of the multiplexer when its output is next switched. In order to reduce the level shifting burden on the amplifier in the pre-charge circuit, each pre-charge circuit input channel has a respective capacitor that is able to be switched in and out of series with the respective multiplexer channels, such that the respective capacitors track the signal levels on the multiplexer channels. The provision of the corresponding capacitors for each MUX channel reduces the input current to the pre-charge amplifier, and allows for the level shifting burden to be taken by the capacitors, leading to more stable and lower power operation.Type: GrantFiled: December 12, 2016Date of Patent: February 23, 2021Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANYInventors: Christopher Peter Hurrell, Sanjay Rajasekhar
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Publication number: 20200382127Abstract: Techniques are described to cancel kT/C sampling noise and residue amplifier sampling noise while also reducing power consumption in a pipelined analog-to-digital converter circuit.Type: ApplicationFiled: February 19, 2019Publication date: December 3, 2020Inventors: Sanjay Rajasekhar, Roberto Maurino
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Patent number: 10715160Abstract: Noise sources in an ADC circuit can include kT/C noise of a sampling capacitor, noise coupling on to sampling capacitors from digital circuits, and amplifier noise. Also, charge injection from mismatch in sample switches can cause offsets. These various noise sources can be largely canceled or reduced using described techniques. As a result, the size of the sampling capacitors can be greatly reduced, while still achieving significantly improved noise performance and power efficiency for the overall converter.Type: GrantFiled: September 13, 2019Date of Patent: July 14, 2020Assignee: Analog Devices International Unlimited CompanyInventors: Sanjay Rajasekhar, Jesper Steensgaard-Madsen, Hongxing Li, Christopher Peter Hurrell
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Patent number: 10409312Abstract: A duty cycled voltage reference circuit is turned on and off synchronously with the operation of a second, reference-consuming, duty-cycled circuit to which it supplies a reference. When the reference consuming circuit no longer has need of the reference, the voltage reference circuit itself is then also powered down. The reference circuit is then powered back up for the next duty cycle sufficiently in advance of the reference consuming circuit such that any auto-zeroing and noise filtering operations required by the reference circuit are complete and a stable reference voltage is output at least simultaneously with, or slightly before, the reference consuming circuit begins to make use of the voltage reference signal. In this manner, synchronous duty-cycled operation of the voltage reference circuit with the reference-consuming circuit is obtained, with the consequence that power consumption by the reference circuit is reduced.Type: GrantFiled: July 19, 2018Date of Patent: September 10, 2019Assignee: Analog Devices Global Unlimited CompanyInventor: Sanjay Rajasekhar
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Patent number: 10128859Abstract: Techniques are described to cancel kT/C sampling noise and residue amplifier sampling noise while also reducing power consumption in a pipelined analog-to-digital converter circuit.Type: GrantFiled: February 20, 2018Date of Patent: November 13, 2018Assignee: Analog Devices Global Unlimited CompanyInventors: Sanjay Rajasekhar, Roberto Sergio Matteo Maurino
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Publication number: 20180167067Abstract: A pre-charge circuit is provided for pre-charging the input node of a capacitive component to which the multiplexer output is fed to a charge level that is close to or approximates the signal output level of the multiplexer when its output is next switched. In order to reduce the level shifting burden on the amplifier in the pre-charge circuit, each pre-charge circuit input channel has a respective capacitor that is able to be switched in and out of series with the respective multiplexer channels, such that the respective capacitors track the signal levels on the multiplexer channels. The provision of the corresponding capacitors for each MUX channel reduces the input current to the pre-charge amplifier, and allows for the level shifting burden to be taken by the capacitors, leading to more stable and lower power operation.Type: ApplicationFiled: December 12, 2016Publication date: June 14, 2018Inventors: Christopher Peter Hurrell, Sanjay Rajasekhar
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Patent number: 9800262Abstract: A sigma delta analog-to-digital converter (ADC) circuit comprises a capacitive gain amplifier circuit having a first input to receive an input voltage and a second input; a loop filter circuit connected to an output of the capacitive gain amplifier circuit; a sub-ADC circuit including an output and an input connected to an output of the loop filter circuit; and a digital-to-analog (DAC) circuit including a DAC input connected to the output of the sub-ADC circuit, and a DAC output connected to the second input of the capacitive gain amplifier.Type: GrantFiled: September 7, 2016Date of Patent: October 24, 2017Assignee: Analog Devices GlobalInventors: Roberto Sergio Matteo Maurino, Sanjay Rajasekhar, Pasquale Delizia, Colin G. Lyden, Gabriel Banarie
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Patent number: 9391628Abstract: An input stage to an analog to digital converter (ADC) includes at least one sampling capacitor (SC) for sampling an input signal in acquire phases, a capacitive gain amplifier (CGA) for providing the input signal to the SC, and bandwidth control means. The bandwidth control means is configured to ensure that the SC has a first bandwidth during a first part of an acquire phase and has a second bandwidth during a subsequent, second, part of said acquire phase, the second bandwidth being smaller than the first. In this manner, first, the input signal is sampled at a higher, first, bandwidth allowing to take advantage of using a high-bandwidth CGA to minimize settling error on the SC, and, next, during a second part of the same acquire phase, the input signal is sampled at a lower, second, bandwidth advantageously decreasing noise resulting from the use of a high-bandwidth CGA.Type: GrantFiled: December 14, 2015Date of Patent: July 12, 2016Assignee: Analog Devices GlobalInventors: Colin G. Lyden, Pasquale Delizia, Sanjay Rajasekhar, Yogesh Jayarman Sharma, Arthur J. Kalb, Marvin L. Shu, Gerard Mora-Puchalt, Roberto S. Maurino
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Patent number: 9294037Abstract: Apparatus and methods for autozero amplifiers are provided herein. In certain configurations, an autozero amplifier includes at least three transconductance stages and an autozero timing control circuit configured to control an autozero sequence of the transconductance stages. The autozero timing control circuit can stagger autozeroing of the transconductance stages, such that a relatively small amount of the amplifier's amplification circuitry is connected to or disconnected from the amplifier's signal path at any given time. For example, in certain configurations, when one of the transconductance stages in autozeroed over a particular time interval, the remaining transconductance stages can operate in parallel to provide amplification during that time interval.Type: GrantFiled: March 24, 2014Date of Patent: March 22, 2016Assignee: Analog Devices GlobalInventors: Roberto S. Maurino, Venkata Aruna Srikanth Nittala, Abhilasha Kawle, Sanjay Rajasekhar
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Publication number: 20150270805Abstract: Apparatus and methods for autozero amplifiers are provided herein. In certain configurations, an autozero amplifier includes at least three transconductance stages and an autozero timing control circuit configured to control an autozero sequence of the transconductance stages. The autozero timing control circuit can stagger autozeroing of the transconductance stages, such that a relatively small amount of the amplifier's amplification circuitry is connected to or disconnected from the amplifier's signal path at any given time. For example, in certain configurations, when one of the transconductance stages in autozeroed over a particular time interval, the remaining transconductance stages can operate in parallel to provide amplification during that time interval.Type: ApplicationFiled: March 24, 2014Publication date: September 24, 2015Applicant: Analog Devices TechnologyInventors: Roberto S. Maurino, Venkata Aruna Srikanth Nittala, Abhilasha Kawle, Sanjay Rajasekhar
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Patent number: 9065463Abstract: A circuit may include a plurality of primary digital-to-analog (DAC) elements for converting a digital input signal into an analog output signal. A control circuit may control each primary DAC element to switch between a first state and a second state based on the digital input signal to provide the analog output signal at an output representing the digital input signal. A plurality of corrective DAC elements may be coupled in parallel to the plurality of primary DAC elements between the control circuit and the output. The plurality of corrective DAC elements may be controlled to mitigate for intersymbol interference (ISI) due to parasitic capacitance in the primary DAC elements. The plurality of corrective DAC elements may not contribute a direct current to the analog output signal.Type: GrantFiled: October 11, 2013Date of Patent: June 23, 2015Assignee: ANALOG DEVICES GLOBALInventor: Sanjay Rajasekhar
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Patent number: 9065477Abstract: A digital-to-analog (DAC) element may include a plurality of switches arranged to form two circuit branches between a current source and a first and a second outputs. The first circuit branch may include two switches defining parallel current paths between the current source and the first output terminal. The second circuit branch may include two switches defining parallel current paths between the current source and the second output terminal. A control circuit, responsive to an input signal that selects one of the circuit branches, may provide control signals to close one of switches in the selected circuit branch in a first portion of a clock cycle and to close the other of the switches in the selected circuit branch in a second portion of the clock cycle.Type: GrantFiled: February 12, 2014Date of Patent: June 23, 2015Assignee: ANALOG DEVICES GLOBALInventors: Sanjay Rajasekhar, Abhilasha Kawle, Roberto S Maurino, Srikanth Nittala
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Publication number: 20150102949Abstract: A circuit may include a plurality of primary digital-to-analog (DAC) elements for converting a digital input signal into an analog output signal. A control circuit may control each primary DAC element to switch between a first state and a second state based on the digital input signal to provide the analog output signal at an output representing the digital input signal. A plurality of corrective DAC elements may be coupled in parallel to the plurality of primary DAC elements between the control circuit and the output. The plurality of corrective DAC elements may be controlled to mitigate for intersymbol interference (ISI) due to parasitic capacitance in the primary DAC elements. The plurality of corrective DAC elements may not contribute a direct current to the analog output signal.Type: ApplicationFiled: October 11, 2013Publication date: April 16, 2015Applicant: Analog Devices TechnologyInventor: Sanjay Rajasekhar
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Publication number: 20150061908Abstract: A digital-to-analog (DAC) element may include a plurality of switches arranged to form two circuit branches between a current source and a first and a second outputs. The first circuit branch may include two switches defining parallel current paths between the current source and the first output terminal. The second circuit branch may include two switches defining parallel current paths between the current source and the second output terminal. A control circuit, responsive to an input signal that selects one of the circuit branches, may provide control signals to close one of switches in the selected circuit branch in a first portion of a clock cycle and to close the other of the switches in the selected circuit branch in a second portion of the clock cycle.Type: ApplicationFiled: February 12, 2014Publication date: March 5, 2015Applicant: ANALOG DEVICES TECHNOLOGYInventors: Sanjay RAJASEKHAR, Abhilasha KAWLE, Roberto S. MAURINO, Srikanth NITTALA
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Publication number: 20140203957Abstract: A continuous time input stage including a first digital-to-analog converter (DAC) including a first DAC code input, a second DAC including a second DAC code input, a first set of switches coupled to the output of the first DAC, a second set of switches coupled to the output of the second DAC, and an amplifier configured to receive the output of either the first DAC or the second DAC.Type: ApplicationFiled: January 22, 2013Publication date: July 24, 2014Applicant: Analog Devices TechnologyInventors: Roberto S. MAURINO, Sanjay RAJASEKHAR, Abhilasha KAWLE
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Patent number: 8779958Abstract: A continuous time input stage including a first digital-to-analog converter (DAC) including a first DAC code input, a second DAC including a second DAC code input, a first set of switches coupled to the output of the first DAC, a second set of switches coupled to the output of the second DAC, and an amplifier configured to receive the output of either the first DAC or the second DAC.Type: GrantFiled: January 22, 2013Date of Patent: July 15, 2014Assignee: Analog Devices TechnologyInventors: Roberto S. Maurino, Sanjay Rajasekhar, Abhilasha Kawle
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Patent number: 8576002Abstract: Embodiments of the present invention provide a sample and hold amplifier that provides a preamplifier with a multi-stage zeroing architecture. The multi-stage architecture reduces effects of parasitic capacitance exponentially over prior attempts, which yields increased accuracy.Type: GrantFiled: July 20, 2011Date of Patent: November 5, 2013Assignee: Analog Devices, Inc.Inventor: Sanjay Rajasekhar
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Publication number: 20120242404Abstract: Embodiments of the present invention provide a sample and hold amplifier that provides a preamplifier with a multi-stage zeroing architecture. The multi-stage architecture reduces effects of parasitic capacitance exponentially over prior attempts, which yields increased accuracy.Type: ApplicationFiled: July 20, 2011Publication date: September 27, 2012Applicant: Analog Devices, Inc.Inventor: Sanjay RAJASEKHAR