Patents by Inventor Sanjay Thekdi
Sanjay Thekdi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6979652Abstract: Openings of variable shape are made sequentially by alternately etching an opening in silicon and depositing a conformal fluorocarbon polymer on the sidewalls. This polymer protects the sidewalls of the opening from further etching. An isotropic etch can be carried out to change the profile of the etched feature, and for lift-off of the etched feature from the silicon substrate.Type: GrantFiled: April 8, 2002Date of Patent: December 27, 2005Assignee: Applied Materials, Inc.Inventors: Anisul Khan, Sharma V Pamarthy, Sanjay Thekdi, Ajay Kumar
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Patent number: 6979640Abstract: A method of making a semiconductor structure comprises forming a hole through a first dielectric layer; followed by forming a hole through an etch-stop layer, to expose a first conducting layer. The thickness of the etch-stop layer is at least one-half the smallest line width of the first conducting layer.Type: GrantFiled: March 29, 2002Date of Patent: December 27, 2005Assignee: Cypress Semiconductor CorporationInventors: Alain Blosse, Sanjay Thekdi
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Publication number: 20050135728Abstract: The invention relates to a variable optical attenuator constructed as a Mach Zehnder planar lightwave circuit, particularly including a channel waveguide support structure for heat isolation and stress relief to reduce polarization dependent loss (PDL) and power consumption in the device. Power reduction trenches comprise longitudinal segments having small stress relief pillars of cladding material left in between them in the etching process. The waveguides of the MZI are supported by a main pillar structure and integral stress relief pillars which remain after removal of the trenches. The waveguide is surrounded by air on three sides for improved heat isolation. The performance of the present invention shows substantial improvement in PDL and extinction ratio over the prior art continuous trench design, and also, to a smaller degree, over the case where power reduction trenches are not used at all.Type: ApplicationFiled: December 17, 2004Publication date: June 23, 2005Applicant: JDS UNIPHASE CORPORATIONInventors: Anca Sala, Duncan Harwood, Barthelemy Fondeur, Anantharaman Vaidyanathan, Robert Brainard, Sanjay Thekdi, Thomas Nguyen, Ian Hutagalung
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Publication number: 20050031968Abstract: The present application relates to a method of fabricating planar circuits using a photolithographic mask set, to the photolithographic mask set, and to a planar circuit fabricated with the photolithographic mask set. The instant invention involves separating a photolithographic mask into two parts, namely, a master mask and one or more slave masks. The master mask and the one or more slave masks form a photolithographic mask set that is used iteratively to fabricate the planar circuits. In particular, the master mask is used as a template to provide the general layout for the planar circuit, while each slave mask is varied to tune and/or tailor the planar circuit. Since only a small portion of the planar circuit is redesigned and/or rewritten as a new mask (i.e., the slave mask), the instant invention provides a simple and cost effective method for optimizing planar circuits.Type: ApplicationFiled: December 15, 2003Publication date: February 10, 2005Applicant: JDS Uniphase CorporationInventors: Barthelemy Fondeur, Anca Sala, Robert Brainard, David Nakamoto, Tom Truong, Sanjay Thekdi, Anantharaman Vaidyanathan
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Patent number: 6696365Abstract: A method of etching high aspect ratio, anisotropic deep trench openings in a silicon substrate coated with a multilayer mask comprising in sequence a pad oxide layer, a silicon nitride layer, a doped or undoped silicon oxide hard mask layer, a polysilicon hard mask layer, an antireflection coating and a patterned photoresist layer in a single chamber comprising patterning the antireflection coating and hard mask layer, removing the photoresist and antireflection layers with oxygen, using the patterned polysilicon as a hard mask layer etching an opening in the silicon oxide hard mask layer, the silicon nitride layer and the pad oxide layer, removing the polysilicon hard mask layer with CF4/CHF3, and etching an anisotropic deep trench in the silicon substrate using the patterned silicon oxide hard mask layer as a mask and an etchant mixture including nitrogen trifluoride that self-cleans the chamber.Type: GrantFiled: January 7, 2002Date of Patent: February 24, 2004Assignee: Applied Materials, Inc.Inventors: Ajay Kumar, Anisul Khan, Sanjay Thekdi, Dragan V. Podlesnik
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Publication number: 20030189024Abstract: Openings of variable shape are made sequentially by alternately etching an opening in silicon and depositing a conformal fluorocarbon polymer on the sidewalls. This polymer protects the sidewalls of the opening from further etching. An isotropic etch can be carried out to change the profile of the etched feature, and for lift-off of the etched feature from the silicon substrate.Type: ApplicationFiled: April 8, 2002Publication date: October 9, 2003Applicant: Applied Materials Inc.Inventors: Anisul Khan, Sharma V. Pamarthy, Sanjay Thekdi, Ajay Kumar
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Publication number: 20030129840Abstract: A method of etching high aspect ratio, anisotropic deep trench openings in a silicon substrate coated with a multilayer mask comprising in sequence a pad oxide layer, a silicon nitride layer, a doped or undoped silicon oxide hard mask layer, a polysilicon hard mask layer, an antireflection coating and a patterned photoresist layer in a single chamber comprising patterning the antireflection coating and hard mask layer, removing the photoresist and antireflection layers with oxygen, using the patterned polysilicon as a hard mask layer etching an opening in the silicon oxide hard mask layer, the silicon nitride layer and the pad oxide layer, removing the polysilicon hard mask layer with CF4/CHF3, and etching an anisotropic deep trench in the silicon substrate using the patterned silicon oxide hard mask layer as a mask and an etchant mixture including nitrogen trifluoride that self-cleans the chamber.Type: ApplicationFiled: January 7, 2002Publication date: July 10, 2003Inventors: Ajay Kumar, Anisul Khan, Sanjay Thekdi, Dragan V. Podlesnik
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Publication number: 20030052088Abstract: Trench and stacked capacitors are commonly used in the construction of DRAMs utilized in electronic devices. Conventional methods of manufacture typically result in capacitor structures having relatively smooth sidewall profiles which are integrated into a capacitor structure. The present invention provides a novel method by which the capacitance density of both trench and stacked capacitors can be increased, without increasing the footprint or depth of the capacitor structure, by increasing the surface area of the sidewall profiles of the capacitor structures using an iterative etch process that comprises an isotropic plasma etching step to achieve an enlarged sidewall profile.Type: ApplicationFiled: September 19, 2001Publication date: March 20, 2003Inventors: Anisul Khan, Ajay Kumar, Sharma Pamarthy, Sanjay Thekdi
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Publication number: 20030052082Abstract: Optical waveguides can be made accurately using conventional semiconductor processing and equipment by forming an opening in a suitable substrate, conformally depositing a first cladding layer in the opening, filling the opening with a core material, removing excess core material, as by chemical mechanical polishing, and depositing a second cladding layer thereover, said first and second cladding layers and said core material each having a different index of refraction. Such optical waveguides can be connected, horizontally and/or vertically, to other devices formed in or on the substrate.Type: ApplicationFiled: September 19, 2001Publication date: March 20, 2003Inventors: Anisul Khan, Ajay Kumar, Sanjay Thekdi
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Patent number: 6372634Abstract: A plasma etch chemistry and etch methodology is provided to improve critical dimension control for openings formed into and/or through a semiconductor thin film. According to an embodiment, the plasma etch chemistry includes an etchant mixture comprising a first etchant of the formula CxHyFz (where x≧2, y≧1 and z≧2) and a second etchant other than the first etchant to form the openings. The relationship of x, y and z may be such that y+z equals an even number ≦2x+2. According to an alternative embodiment, the plasma etch chemistry further includes strained cyclic (hydro)fluorocarbon. The plasma etch chemistry may be used to form openings in the layer in a single-etch step. In a further embodiment, the plasma etch chemistry described herein may etch less than the entire thickness of the layer, and a second plasma etch chemistry substantially free of the first etchant and strained cyclic (hydro)fluorocarbons etches the remainder of the layer to form the openings.Type: GrantFiled: June 15, 1999Date of Patent: April 16, 2002Assignee: Cypress Semiconductor Corp.Inventors: Jianmin Qiao, Sanjay Thekdi, Manuj Rathor, James E. Nulty
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Patent number: 6322716Abstract: A method for conditioning a plasma etch chamber is presented. A plasma etch chamber is provided, which preferably includes a chuck for supporting a topography. A conditioning process may be performed in the etch chamber. The conditioning process preferably includes positioning a cover topography on or above the chuck. A conditioning feed gas containing (hydro)halocarbons may be introduced into the chamber. A conditioning plasma may be generated from the conditioning feed gas for a conditioning time. Immediately after generating the conditioning plasma is complete, the overall thickness of the cover topography is preferably at least as great as immediately before generating the conditioning plasma. By performing a conditioning process in such a manner, the total cost and complexity of the conditioning process may be reduced.Type: GrantFiled: August 30, 1999Date of Patent: November 27, 2001Assignee: Cypress Semiconductor Corp.Inventors: Jianmin Qiao, Sanjay Thekdi