Patents by Inventor Sanjeev B. Sathe
Sanjeev B. Sathe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7186590Abstract: An electronic package having one or more components comprising: a substrate having a first coefficient of thermal expansion; a lid attached to the substrate, the lid including a vapor chamber, the lid having a second coefficient of thermal expansion, the first coefficient of thermal expansion matched to the second coefficient of expansion; a thermal transfer medium in contact with a back surface of each component and an outer surface of a lower wall of the lid; and each component electrically connected to a top surface of the substrate.Type: GrantFiled: September 18, 2003Date of Patent: March 6, 2007Assignee: International Business Machines CorporationInventors: David J. Alcoe, William L. Brodsky, Varaprasad V. Calmidi, Sanjeev B. Sathe, Randall J. Stutzman
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Patent number: 7183642Abstract: Removing heat generated by an operating IC chip from both the chip and the electronics package containing the chip is essential for proper system operation and to increase the life of the electronics package. Using an air permeable lid with the electronic package increases the heat transfer away from the IC chip and electronics package, thereby cooling the chip and the package.Type: GrantFiled: September 11, 2002Date of Patent: February 27, 2007Assignee: International Business Machines CorporationInventors: Anandaroop Bhattacharya, Varaprasad V. Calmidi, Sanjeev B. Sathe
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Patent number: 7037753Abstract: A semiconductor chip package having a non-planar chip therein, to reduce the stress concentrations between the chip and cover plate. In particular, a chip and method of forming a chip having a non-planar or “domed” back surface, wherein the thickness of the non-planar chip is greatest substantially near the center of the chip. Further, a method of rounding the edges or corners of the chip to reduce crack propagation originating at the edges of the chip.Type: GrantFiled: January 8, 2004Date of Patent: May 2, 2006Assignee: International Business Machines CorporationInventors: William L. Brodsky, Sanjeev B. Sathe, George H. Thiel
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Patent number: 6992379Abstract: An electronic package and method of making same in which a circuitized substrate having a first stiffness includes a plurality of electrically conductive circuit members on a first portion of the circuitized substrate and is adapted for having solder connections thereon and for being electrically connected to a semiconductor chip. A stiffener layer having a second stiffness is positioned on a second portion of the circuitized substrate relative to the first portion, the second stiffness of the stiffener layer distributing a portion of the first stiffness of said circuitized substrate so as to substantially prevent failure of the solder connections between the electrically conductive circuit members and the semiconductor chip during operation of the electronic package.Type: GrantFiled: September 5, 2001Date of Patent: January 31, 2006Assignee: International Business Machines CorporationInventors: David J. Alcoe, Li Li, Sanjeev B. Sathe
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Patent number: 6989607Abstract: A method and structure to electrically couple a semiconductor device to a substrate that is divided into a plurality of segments. Alternatively, a semiconductor device may be divided into a plurality of segments and the plurality of segments are electrically coupled to a single substrate.Type: GrantFiled: July 29, 2003Date of Patent: January 24, 2006Assignee: International Business Machines CorporationInventors: Krishna Darbha, Miguel A. Jimarez, Matthew M. Reiss, Sanjeev B. Sathe, Charles G. Woychik
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Patent number: 6967389Abstract: A semiconductor chip module and forming method is provided. The module includes a support member having at least one well being open to receive a semiconductor chip. Each well depth is substantially equal to the thickness of a chip. The support member has a planar region surrounding each well. A chip is in each well. A dielectric sheet of material is laminated over each chip and extends onto the planar area surrounding the wells and has a face oriented away from the chip. Electrical circuitry including capture pads is formed on the face of the dielectric sheet and extends onto the sheet that overlies the planar region. Conducting vias are formed in the dielectric sheet connecting the electrical circuitry on the dielectric sheet with the contact pads on the chip. A multilayer, circuitized laminate having a fan-out pattern is laminated to the dielectric sheet.Type: GrantFiled: December 23, 2003Date of Patent: November 22, 2005Assignee: International Business Machines CorporationInventors: William Infantolino, Voya R. Markovich, Sanjeev B. Sathe, George H. Thiel
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Publication number: 20040142508Abstract: A semiconductor chip package having a non-planar chip therein, to reduce the stress concentrations between the chip and cover plate. In particular, a chip and method of forming a chip having a non-planar or “domed” back surface, wherein the thickness of the non-planar chip is greatest substantially near the center of the chip. Further, a method of rounding the edges or corners of the chip to reduce crack propagation originating at the edges of the chip.Type: ApplicationFiled: January 8, 2004Publication date: July 22, 2004Inventors: William L. Brodsky, Sanjeev B. Sathe, George H. Thiel
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Publication number: 20040135245Abstract: A semiconductor chip module and forming method is provided. The module includes a support member having at least one well being open to receive a semiconductor chip. Each well depth is substantially equal to the thickness of a chip. The support member has a planar region surrounding each well. A chip is in each well. A dielectric sheet of material is laminated over each chip and extends onto the planar area surrounding the wells and has a face oriented away from the chip. Electrical circuitry including capture pads is formed on the face of the dielectric sheet and extends onto the sheet that overlies the planar region. Conducting vias are formed in the dielectric sheet connecting the electrical circuitry on the dielectric sheet with the contact pads on the chip. A multilayer, circuitized laminate having a fan-out pattern is laminated to the dielectric sheet.Type: ApplicationFiled: December 23, 2003Publication date: July 15, 2004Applicant: International Business Machines CorporationInventors: William Infantolino, Voya R. Markovich, Sanjeev B. Sathe, George H. Thiel
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Patent number: 6759270Abstract: A semiconductor chip module and forming method is provided. The module includes a support member having at least one well being open to receive a semiconductor chip. Each well depth is substantially equal to the thickness of a chip. The support member has a planar region surrounding each well. A chip is in each well. A dielectric sheet of material is laminated over each chip and extends onto the planar area surrounding the wells and has a face oriented away from the chip. Electrical circuitry including capture pads is formed on the face of the dielectric sheet and extends onto the sheet that overlies the planar region. Conducting vias are formed in the dielectric sheet connecting the electrical circuitry on the dielectric sheet with the contact pads on the chip. A multilayer, circuitized laminate having a fan-out pattern is laminated to the dielectric sheet.Type: GrantFiled: September 11, 2003Date of Patent: July 6, 2004Assignee: International Buisness Machines CorporationInventors: William Infantolino, Voya R. Markovich, Sanjeev B. Sathe, George H. Thiel
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Patent number: 6756662Abstract: A semiconductor chip module and forming method is provided. The module includes a support member having at least one well being open to receive a semiconductor chip. Each well depth is substantially equal to the thickness of a chip. The support member has a planar region surrounding each well. A chip is in each well. A dielectric sheet of material is laminated over each chip and extends onto the planar area surrounding the wells and has a face oriented away from the chip. Electrical circuitry including capture pads is formed on the face of the dielectric sheet and extends onto the sheet that overlies the planar region. Conducting vias are formed in the dielectric sheet connecting the electrical circuitry on the dielectric sheet with the contact pads on the chip. A multilayer, circuitized laminate having a fan-out pattern is laminated to the dielectric sheet.Type: GrantFiled: September 25, 2002Date of Patent: June 29, 2004Assignee: International Business Machines CorporationInventors: William Infantolino, Voya R. Markovich, Sanjeev B. Sathe, George H. Thiel
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Patent number: 6731012Abstract: A semiconductor chip package having a non-planar chip therein, to reduce the stress concentrations between the chip and cover plate. In particular, a chip and method of forming a chip having a non-planar or “domed” back surface, wherein the thickness of the non-planar chip is greatest substantially near the center of the chip. Further, a method of rounding the edges or corners of the chip to reduce crack propagation originating at the edges of the chip.Type: GrantFiled: December 23, 1999Date of Patent: May 4, 2004Assignee: International Business Machines CorporationInventors: William L. Brodsky, Sanjeev B. Sathe, George H. Thiel
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Publication number: 20040057214Abstract: An electronic package having one or more components comprising: a substrate having a first coefficient of thermal expansion; a lid attached to the substrate, the lid including a vapor chamber, the lid having a second coefficient of thermal expansion, the first coefficient of thermal expansion matched to the second coefficient of expansion; a thermal transfer medium in contact with a back surface of each component and an outer surface of a lower wall of the lid; and each component electrically connected to a top surface of the substrate.Type: ApplicationFiled: September 18, 2003Publication date: March 25, 2004Inventors: David J. Alcoe, William L. Brodsky, Varaprasad V. Calmidi, Sanjeev B. Sathe, Randall J. Stutzman
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Publication number: 20040056347Abstract: A semiconductor chip module and forming method is provided. The module includes a support member having at least one well being open to receive a semiconductor chip. Each well depth is substantially equal to the thickness of a chip. The support member has a planar region surrounding each well. A chip is in each well. A dielectric sheet of material is laminated over each chip and extends onto the planar area surrounding the wells and has a face oriented away from the chip. Electrical circuitry including capture pads is formed on the face of the dielectric sheet and extends onto the sheet that overlies the planar region. Conducting vias are formed in the dielectric sheet connecting the electrical circuitry on the dielectric sheet with the contact pads on the chip. A multilayer, circuitized laminate having a fan-out pattern is laminated to the dielectric sheet.Type: ApplicationFiled: September 25, 2002Publication date: March 25, 2004Applicant: International Business Machines CorporationInventors: William Infantolino, Voya R. Markovich, Sanjeev B. Sathe, George H. Thiel
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Publication number: 20040058474Abstract: A semiconductor chip module and forming method is provided. The module includes a support member having at least one well being open to receive a semiconductor chip. Each well depth is substantially equal to the thickness of a chip. The support member has a planar region surrounding each well. A chip is in each well. A dielectric sheet of material is laminated over each chip and extends onto the planar area surrounding the wells and has a face oriented away from the chip. Electrical circuitry including capture pads is formed on the face of the dielectric sheet and extends onto the sheet that overlies the planar region. Conducting vias are formed in the dielectric sheet connecting the electrical circuitry on the dielectric sheet with the contact pads on the chip. A multilayer, circuitized laminate having a fan-out pattern is laminated to the dielectric sheet.Type: ApplicationFiled: September 11, 2003Publication date: March 25, 2004Applicant: International Business Machines CorporationInventors: William Infantolino, Voya R. Markovich, Sanjeev B. Sathe, George H. Thiel
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Publication number: 20040046249Abstract: Removing heat generated by an operating IC chip from both the chip and the electronics package containing the chip is essential for proper system operation and to increase the life of the electronics package. Using an air permeable lid with the electronic package increases the heat transfer away from the IC chip and electronics package, thereby cooling the chip and the package.Type: ApplicationFiled: September 11, 2002Publication date: March 11, 2004Applicant: International Business Machines CorporationInventors: Anandaroop Bhattacharya, Varaprasad V. Calmidi, Sanjeev B. Sathe
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Publication number: 20040021205Abstract: A method and structure to electrically couple a semiconductor device to a substrate that is divided into a plurality of segments. Alternatively, a semiconductor device may be divided into a plurality of segments and the plurality of segments are electrically coupled to a single substrate.Type: ApplicationFiled: July 29, 2003Publication date: February 5, 2004Inventors: Krishna Darbha, Miguel A. Jimarez, Matthew M. Reiss, Sanjeev B. Sathe, Charles G. Woychik
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Patent number: 6665187Abstract: An electronic package having one or more components comprising: a substrate having a first coefficient of thermal expansion; a lid attached to the substrate, the lid including a vapor chamber, the lid having a second coefficient of thermal expansion, the first coefficient of thermal expansion matched to the second coefficient of expansion; a thermal transfer medium in contact with a back surface of each component and an outer surface of a lower wall of the lid; and each component electrically connected to a top surface of the substrate.Type: GrantFiled: July 16, 2002Date of Patent: December 16, 2003Assignee: International Business Machines CorporationInventors: David J. Alcoe, William L. Brodsky, Varaprasad V. Calmidi, Sanjeev B. Sathe, Randall J. Stutzman
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Patent number: 6639302Abstract: A method and structure to electrically couple a semiconductor device to a substrate that is divided into a plurality of segments. Alternatively, a semiconductor device may be divided into a plurality of segments and the plurality of segments are electrically coupled to a single substrate.Type: GrantFiled: March 20, 2002Date of Patent: October 28, 2003Assignee: International Business Machines CorporationInventors: Krishna Darbha, Miguel A. Jimarez, Matthew M. Reiss, Sanjeev B. Sathe, Charles G. Woychik
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Publication number: 20030178649Abstract: A method and structure to electrically couple a semiconductor device to a substrate that is divided into a plurality of segments. Alternatively, a semiconductor device may be divided into a plurality of segments and the plurality of segments are electrically coupled to a single substrate.Type: ApplicationFiled: March 20, 2002Publication date: September 25, 2003Applicant: International Business Machines CorporationInventors: Krishna Darbha, Miguel A. Jimarez, Matthew M. Reiss, Sanjeev B. Sathe, Charles G. Woychik
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Patent number: 6622786Abstract: A heat sink structure is formed by stacking a plurality of heat sink layers. Each layer comprises an array of vertically disposed heat dissipating elements extending from a base plate. Cut outs are formed in each of the base plates to form openings so that when the layers are stacked, each of the ascending successive layers has a larger opening than the layer upon which it rests. Cooling may be by forced air or natural convection. With forced air, air impinges on the top of the stack and into the opening in the base plates. Because of diminishing size of the openings in the stack, a portion of the air is forced out the sides of each layer. With natural convection, air is drawn into the sides of each layer and the hot air at the center flows upwardly through the openings with increasing volume as it rises.Type: GrantFiled: April 17, 2002Date of Patent: September 23, 2003Assignee: International Business Machines CorporationInventors: Varaprasad V. Calmidi, Krishna Darbha, Sanjeev B. Sathe, Jamil A. Wakil