Patents by Inventor Sanjeev K. Maheshwari
Sanjeev K. Maheshwari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230412132Abstract: Low noise voltage generation circuitry includes a voltage source, a low-pass filter with one or more filter stages, and an amplifier selectively coupled to the filter stages. Each filter stage includes a resistor and a pair of capacitors of equal capacitance. The amplifier has an input selectively coupled to an output port of the voltage generation circuitry and has an output selectively coupled to the pair of capacitors in each filter stage. During a sensing phase, the amplifier senses the voltage at the output port. During a first charging phase, the amplifier has a first polarity and charges one of the pair of capacitors in each filter stage. During a second charging phase, the amplifier has a second polarity and charges another one of the pair of capacitors in each filter stage. During a final phase, the pair of capacitors within each filter stage are shorted together to cancel out an amplifier offset while the output port instantaneously settles to the target voltage.Type: ApplicationFiled: June 16, 2022Publication date: December 21, 2023Inventors: Wenbo Liu, Shang Hsien Meng, Sanjeev K. Maheshwari
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Publication number: 20230387898Abstract: A serial data receiver subsystem included in a computer system may include a data detection circuit, a speed detection circuit, and a receiver circuit that includes multiple subcircuits. The data detection circuit performs a comparison a reference voltage to the magnitude of signals received via a communication link that encode a serial data stream consisting of multiple data symbols. Using a result of the comparison, the data detection circuit may activate a indicating the presence of data on the communication link. Once the is active, the speed detection circuit checks the number of transitions to determine a rate at which data is being transmitted. In response to a determination that the rate of the data being transmitted exceeds a threshold value, the receiver circuit activates one or more of the multiple subcircuits.Type: ApplicationFiled: August 31, 2022Publication date: November 30, 2023Inventors: Vishal Varma, Dhaval H. Shah, Jose A. Tierno, Sanjeev K. Maheshwari, Sumeet Gupta
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Patent number: 11770274Abstract: A decision feedback equalizer (DFE) sampler circuit is disclosed. The DFE sampler includes a front-end circuit configured to generate a filtered signal using a plurality of signals that encode a serial data stream that includes a plurality of data symbols and a summing circuit configured to generate an equalized signal by combining the filtered signal and an analog feedback signal based on a digital feedback signal. The DFE sampler further includes first and second samplers configured to sample the equalized signal and generate first and second regeneration signals, respectively, during first and second time periods. A compensation circuit is configured to generate the digital feedback signal using the first and second regeneration signals. The first and second samplers, in alternating time periods, cancel ISI from the equalized signal using the first and second regeneration signals, respectively.Type: GrantFiled: May 24, 2022Date of Patent: September 26, 2023Assignee: Apple Inc.Inventors: Wing Liu, Sanjeev K. Maheshwari
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Patent number: 11757681Abstract: To compensate for intersymbol interference, a serial data receiver circuit included in a computer system may include an equalizer circuit that includes a digital-to-analog converter circuit. Based on previously received symbols, the equalizer circuit modifies a signal received via a communication channel or link prior to clock and data recovery. In cases when the digital-to-analog converter circuit becomes saturated, the equalizer circuit additionally uses a dither signal to modify the received signal.Type: GrantFiled: September 23, 2022Date of Patent: September 12, 2023Assignee: Apple Inc.Inventors: Jose A. Tierno, Haiming Jin, Brian S. Leibowitz, Sanjeev K. Maheshwari, Chintan S. Thakkar
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Patent number: 11664809Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.Type: GrantFiled: April 5, 2021Date of Patent: May 30, 2023Assignee: Apple Inc.Inventors: Jaeduk Han, Wenbo Liu, Wing Liu, Ming-Shuan Chen, Sanjeev K. Maheshwari, Vishal Varma, Sunil Bhosekar, Lizhi Zhong, Gary A. Rogan
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Patent number: 11619959Abstract: A voltage regulator circuit included in a computer system may include a switch device coupled between an input power supply node and a regulated power supply node. The switch device may change a value of a supply current flowing from the input power supply node and the regulated power supply node to regulate a voltage level of the regulated power supply node. A noise cancelation current may be feed forward onto a control terminal of the switch device to cancel noise on the regulated power supply node resulting from noise present on the input power supply node.Type: GrantFiled: September 23, 2020Date of Patent: April 4, 2023Assignee: Apple Inc.Inventors: Gokce Gurun, Sanjeev K. Maheshwari, Wenbo Liu
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Patent number: 11586240Abstract: Embodiments relate to a circuit implementation for controlling a delay of a clock signal. The clock delay control circuit includes a sensing circuit and a phase interpolator controlled by the sensing circuit. The sensing circuit generates a first control signal that increases when a level of a supply voltage increases, and decreases when the level of the supply voltage decreases. Moreover, the sensing circuit generates a second control signal that decreases when the level of the supply voltage increases, and increases when the level of the supply voltage decreases. The phase interpolator includes multiple paths, each having a different propagation delay. The coupling between each path and the output node of the phase interpolator is controlled by the control signals generated by the sensing circuit.Type: GrantFiled: July 18, 2022Date of Patent: February 21, 2023Assignee: Apple Inc.Inventors: Bo Sun, Brian S. Leibowitz, Jafar Savoj, Sanjeev K. Maheshwari
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Patent number: 11392163Abstract: Embodiments relate to a circuit implementation for controlling a delay of a clock signal. The clock delay control circuit includes a sensing circuit and a phase interpolator controlled by the sensing circuit. The sensing circuit generates a first control signal that increases when a level of a supply voltage increases, and decreases when the level of the supply voltage decreases. Moreover, the sensing circuit generates a second control signal that decreases when the level of the supply voltage increases, and increases when the level of the supply voltage decreases. The phase interpolator includes multiple paths, each having a different propagation delay. The coupling between each path and the output node of the phase interpolator is controlled by the control signals generated by the sensing circuit.Type: GrantFiled: September 23, 2021Date of Patent: July 19, 2022Assignee: Apple Inc.Inventors: Bo Sun, Brian S. Leibowitz, Jafar Savoj, Sanjeev K. Maheshwari
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Publication number: 20220091622Abstract: A voltage regulator circuit included in a computer system may include a switch device coupled between an input power supply node and a regulated power supply node. The switch device may change a value of a supply current flowing from the input power supply node and the regulated power supply node to regulate a voltage level of the regulated power supply node. A noise cancelation current may be feed forward onto a control terminal of the switch device to cancel noise on the regulated power supply node resulting from noise present on the input power supply node.Type: ApplicationFiled: September 23, 2020Publication date: March 24, 2022Inventors: Gokce Gurun, Sanjeev K. Maheshwari, Wenbo Liu
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Publication number: 20210226639Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.Type: ApplicationFiled: April 5, 2021Publication date: July 22, 2021Inventors: Jaeduk Han, Wenbo Liu, Wing Liu, Ming-Shuan Chen, Sanjeev K. Maheshwari, Vishal Varma, Sunil Bhosekar, Lizhi Zhong, Gary A. Rogan
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Patent number: 11063600Abstract: A multi-stage clock generation circuit is disclosed. The circuit includes first and second ring oscillators. The ring oscillators include a corresponding plurality of delay elements coupled in series, with a plurality of shunt circuits in parallel with corresponding inverters. The shunt circuits include respective interpolation nodes, which are resistively coupled to input and output nodes of their corresponding inverters. The interpolation nodes of the first ring oscillator are coupled to delay element input and output nodes of the second ring oscillator. Similarly, the interpolation nodes of the second ring oscillator are coupled to delay element input and output nodes of the first ring oscillator.Type: GrantFiled: July 15, 2020Date of Patent: July 13, 2021Assignee: Apple Inc.Inventors: Wenbo Liu, Wei-Ming Lee, Sanjeev K. Maheshwari
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Patent number: 11023403Abstract: A system and method for efficiently transporting data across lanes. A computing system includes an interconnect with lanes for transporting data between a source and a destination. When a source receives an indication of a bandwidth requirement change from a first data rate to a second data rate, the transmitter in the source sends messages to the receiver in the destination. The messages indicate that the data rate is going to change and reconfiguration of one or more lanes will be performed. The transmitter selects one or more lanes for transporting data at the second data rate. The transmitter maintains data transport at the first data rate while reconfiguring the selected one or more lanes to the second data rate. After completing the reconfiguration, the transmitter transports data at the second data rate on the selected one or more lanes while preventing data transport on any unselected lanes.Type: GrantFiled: December 2, 2019Date of Patent: June 1, 2021Assignee: Apple Inc.Inventors: Jafar Savoj, Jose A. Tierno, Sanjeev K. Maheshwari, Brian S. Leibowitz, Pradeep R. Trivedi, Gin Yee, Emerson S. Fang
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Patent number: 10972107Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.Type: GrantFiled: July 31, 2019Date of Patent: April 6, 2021Assignee: Apple Inc.Inventors: Jaeduk Han, Wenbo Liu, Wing Liu, Ming-Shuan Chen, Sanjeev K. Maheshwari, Vishal Varma, Sunil Bhosekar, Lizhi Zhong, Gary A. Rogan
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Publication number: 20210036707Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.Type: ApplicationFiled: July 31, 2019Publication date: February 4, 2021Inventors: Jaeduk Han, Wenbo Liu, Wing Liu, Ming-Shuan Chen, Sanjeev K. Maheshwari, Vishal Varma, Sunil Bhosekar, Lizhi Zhong, Gary A. Rogan
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Publication number: 20200183874Abstract: A system and method for efficiently transporting data across lanes. A computing system includes an interconnect with lanes for transporting data between a source and a destination. When a source receives an indication of a bandwidth requirement change from a first data rate to a second data rate, the transmitter in the source sends messages to the receiver in the destination. The messages indicate that the data rate is going to change and reconfiguration of one or more lanes will be performed. The transmitter selects one or more lanes for transporting data at the second data rate. The transmitter maintains data transport at the first data rate while reconfiguring the selected one or more lanes to the second data rate. After completing the reconfiguration, the transmitter transports data at the second data rate on the selected one or more lanes while preventing data transport on any unselected lanes.Type: ApplicationFiled: December 2, 2019Publication date: June 11, 2020Inventors: Jafar Savoj, Jose A. Tierno, Sanjeev K. Maheshwari, Brian S. Leibowitz, Pradeep R. Trivedi, Gin Yee, Emerson S. Fang
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Patent number: 10521391Abstract: A system and method for efficiently transporting data across lanes. A computing system includes an interconnect with lanes for transporting data between a source and a destination. When a source receives an indication of a bandwidth requirement change from a first data rate to a second data rate, the transmitter in the source sends messages to the receiver in the destination. The messages indicate that the data rate is going to change and reconfiguration of one or more lanes will be performed. The transmitter selects one or more lanes for transporting data at the second data rate. The transmitter maintains data transport at the first data rate while reconfiguring the selected one or more lanes to the second data rate. After completing the reconfiguration, the transmitter transports data at the second data rate on the selected one or more lanes while preventing data transport on any unselected lanes.Type: GrantFiled: November 29, 2018Date of Patent: December 31, 2019Assignee: Apple Inc.Inventors: Jafar Savoj, Jose A. Tierno, Sanjeev K. Maheshwari, Brian S. Leibowitz, Pradeep R. Trivedi, Gin Yee, Emerson S. Fang
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Patent number: 10277230Abstract: Techniques are disclosed relating to clock and data recovery circuitry. In some embodiments, a slicing circuit may be configured to sample an input signal to generate a first and second sampled data signal. In some embodiments, a phase detector circuit may be configured to compare the phases of the first and second sampled data signals. In some embodiments, a first charge pump may be configured to supply a first current to a circuit node, and a second charge pump may be configured to supply a second current to the circuit node. In some embodiments, a voltage-controlled oscillator may be configured to adjust a frequency of first and second clock signals based on a voltage of the circuit node.Type: GrantFiled: September 25, 2017Date of Patent: April 30, 2019Assignee: Apple Inc.Inventors: Wenbo Liu, Ming-Shuan Chen, Sanjeev K. Maheshwari
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Publication number: 20190097638Abstract: Techniques are disclosed relating to clock and data recovery circuitry. In some embodiments, a slicing circuit may be configured to sample an input signal to generate a first and second sampled data signal. In some embodiments, a phase detector circuit may be configured to compare the phases of the first and second sampled data signals. In some embodiments, a first charge pump may be configured to supply a first current to a circuit node, and a second charge pump may be configured to supply a second current to the circuit node. In some embodiments, a voltage-controlled oscillator may be configured to adjust a frequency of first and second clock signals based on a voltage of the circuit node.Type: ApplicationFiled: September 25, 2017Publication date: March 28, 2019Inventors: Wenbo Liu, Ming-Shuan Chen, Sanjeev K. Maheshwari
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Publication number: 20100171547Abstract: A pseudo bandgap voltage reference circuit includes a first transistor and a second transistor, each coupled to a supply voltage node. The circuit also includes an amplifier circuit coupled to a gate terminal of each of the first and the second transistors, a current source coupled to the supply voltage node, and a first diode coupled between the current source and a ground reference node. A first input of the amplifier circuit is coupled to a node between the current source and the first diode. In addition, a first terminal of the first transistor is coupled to a second input of the amplifier circuit in a feedback loop. Also, an output reference voltage is developed at an output node coupled to a second terminal of the second transistor. Further, an output current of the current source is independent of a current flowing through the first terminal of the first transistor.Type: ApplicationFiled: January 7, 2009Publication date: July 8, 2010Inventors: Emerson S. Fang, Tin Tin Wee, Sanjeev K. Maheshwari
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Patent number: 7205797Abstract: A single ended input circuit can receive an input signal and generate a correction voltage corresponding to a common mode voltage of the input signal. A comparison of the input signal can be adjusted in response to the correction voltage. In one arrangement, an input circuit (100) can include a compare section (102) with first input (104-0) and second input (104-1). The first input (104-0) can receive an input signal (IN). The second input (104-1) can receive a reference voltage generated by a common mode detect and hold (CMDH) section (106). A (CMDH) section (106) can include an integrator circuit (108), an analog-to-digital (A/D) converter circuit (110), a digital hold circuit (112), and a digital-to-analog (D/A) converter (114). A correction voltage generated by integrating the input signal can be applied as the generated reference voltage.Type: GrantFiled: May 24, 2004Date of Patent: April 17, 2007Assignee: Cypress Semiconductor CorporationInventors: Sanjeev K. Maheshwari, Babak Taheri