Patents by Inventor Sanjib Mallick

Sanjib Mallick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11954344
    Abstract: An apparatus comprises at least one processing device. The at least one processing device is configured, for each of a plurality of logical storage devices of a storage system, to determine in a multi-path layer of a layered software stack of a host device a performance level for that logical storage device, to communicate the performance levels for respective ones of the logical storage devices from the multi-path layer of the layered software stack of the host device to at least one additional layer of the software stack above the multi-path layer, and to select particular ones of the logical storage devices for assignment to particular storage roles in the additional layer based at least in part on the communicated performance levels. The additional layer in some embodiments comprises an application layer configured to automatically select a particular one of the logical storage devices for a particular storage role.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: April 9, 2024
    Assignee: EMC IP Holding Company LLC
    Inventors: Sanjib Mallick, Vinay G. Rao, Jay Jung, Arieh Don
  • Publication number: 20240103729
    Abstract: A processing device illustratively includes a processor coupled to a memory, and is configured to initiate a background copy process in a host device to copy data from a first storage system to a second storage system. The processing device receives input-output (IO) processing pressure feedback from at least one of the first and second storage systems, and adjusts one or more characteristics of the background copy process based at least in part on the received IO processing pressure feedback. The processing device may comprise, for example, host level mirroring (HLM) logic configured to control execution of the background copy process for one or more logical storage devices. Adjusting one or more characteristics of the background copy process based at least in part on the received IO processing pressure feedback may comprise, for example, reducing a rate of the background copy process responsive to the received IO processing pressure feedback.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 28, 2024
    Inventors: Sanjib Mallick, Vinay G. Rao, Arieh Don
  • Publication number: 20240103724
    Abstract: At least one processing device is configured to control delivery of input-output (TO) operations from a host device to a storage system over selected ones of a plurality of paths through a network. The at least one processing device is further configured to designate one or more of the paths as being associated with a link performance issue, to temporarily suspend utilization of the one or more designated paths for delivery of IO operations from the host device to the storage system, to detect a configuration change that is indicative of potential resolution of the link performance issue, and to resume utilization of the one or more designated paths responsive to the detected configuration change. The at least one processing device illustratively comprises a multi-path input-output (MPIO) driver of the host device.
    Type: Application
    Filed: September 23, 2022
    Publication date: March 28, 2024
    Inventors: Sanjib Mallick, Vinay G. Rao, Anthony D. Fong, Scott Rowlands, Arieh Don
  • Patent number: 11934679
    Abstract: A method, computer program product, and computing system for dividing a volume into a plurality of segments. The plurality of segments may be assigned to a plurality of nodes of a multi-node storage system. One or more input/output (IO) request paths for accessing the plurality of segments may be defined based upon, at least in part, assigning the plurality of segments to the plurality of nodes.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: March 19, 2024
    Assignee: EMC IP Holding Company, LLC
    Inventors: David Meiri, Vinay G. Rao, Sanjib Mallick
  • Patent number: 11934659
    Abstract: A processing device illustratively includes a processor coupled to a memory, and is configured to initiate a background copy process in a host device to copy data from a first storage system to a second storage system. The processing device receives input-output (IO) processing pressure feedback from at least one of the first and second storage systems, and adjusts one or more characteristics of the background copy process based at least in part on the received IO processing pressure feedback. The processing device may comprise, for example, host level mirroring (HLM) logic configured to control execution of the background copy process for one or more logical storage devices. Adjusting one or more characteristics of the background copy process based at least in part on the received IO processing pressure feedback may comprise, for example, reducing a rate of the background copy process responsive to the received IO processing pressure feedback.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: March 19, 2024
    Assignee: Dell Products L.P.
    Inventors: Sanjib Mallick, Vinay G. Rao, Arieh Don
  • Publication number: 20240069945
    Abstract: An apparatus in an illustrative embodiment comprises at least one processing device configured to establish a first number of paths to a logical storage volume, stored across multiple storage nodes of a distributed storage system, in a first layer of a software stack of the at least one processing device, and to present a second number of paths to the logical storage volume from the first layer of the software stack to at least one overlying layer of the software stack, the second number of paths being less than the first number of paths. The at least one processing device is further configured to receive input-output operations from the at least one overlying layer of the software stack for delivery to the storage nodes, and to select in the first layer a plurality of paths within the first number of paths to deliver the input-output operations to the storage nodes.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Inventors: Sanjib Mallick, Amit Pundalik Anchi
  • Publication number: 20240061609
    Abstract: An apparatus in one embodiment comprises at least one processing device that includes a processor coupled to a memory. The processing device is configured to obtain buffer availability information from a storage system, the buffer availability information indicating that the storage system is currently experiencing a deficiency in a number of available buffers of a given one of at least first and second different buffer sizes supported by the storage system, and to select particular input-output operations for delivery to the storage system over one or more networks based at least in part on the obtained buffer availability information. Obtaining the buffer availability information from the storage system illustratively comprises sending at least one command from a host device to the storage system. First and second different buffer types having the first and second different buffer sizes may comprise respective different write buffer types within a larger write buffer.
    Type: Application
    Filed: August 16, 2022
    Publication date: February 22, 2024
    Inventors: Sanjib Mallick, Vinay G. Rao, Krishna Deepak Nuthakki, Arieh Don
  • Patent number: 11886711
    Abstract: An apparatus comprises at least one processing device. The at least one processing device is configured to identify at least one logical storage device that has a first service level objective and is exhibiting a deficiency in one or more performance metrics, to identify one or more additional logical storage devices each having a second service level objective lower than the first service level objective and not exhibiting a deficiency in the one or more performance metrics, to generate at least one false-positive signal specifying the one or more additional logical storage devices as each exhibiting a deficiency in the one or more performance metrics, and to provide the at least one false-positive signal to at least one host device. The at least one host device is configured to respond to the at least one false-positive signal by throttling input-output operations for the one or more additional logical storage devices.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: January 30, 2024
    Assignee: Dell Products L.P.
    Inventors: Sanjib Mallick, Vinay G. Rao, Jaeyoo Jung, Arieh Don
  • Publication number: 20230409199
    Abstract: An apparatus comprises at least one processing device. The at least one processing device is configured to identify at least one logical storage device that has a first service level objective and is exhibiting a deficiency in one or more performance metrics, to identify one or more additional logical storage devices each having a second service level objective lower than the first service level objective and not exhibiting a deficiency in the one or more performance metrics, to generate at least one false-positive signal specifying the one or more additional logical storage devices as each exhibiting a deficiency in the one or more performance metrics, and to provide the at least one false-positive signal to at least one host device. The at least one host device is configured to respond to the at least one false-positive signal by throttling input-output operations for the one or more additional logical storage devices.
    Type: Application
    Filed: June 16, 2022
    Publication date: December 21, 2023
    Inventors: Sanjib Mallick, Vinay G. Rao, Jaeyoo Jung, Arieh Don
  • Patent number: 11829602
    Abstract: An apparatus includes at least one processing device configured to obtain information characterizing which of a plurality of storage nodes of a distributed storage system stores respective ones of a plurality of different logical blocks of a logical storage volume of the distributed storage system. The at least one processing device is further configured, for each of a plurality of input-output operations directed to a particular one of the logical blocks of the logical storage volume, to identify, based at least in part on the obtained information, which of the plurality of storage nodes of the distributed storage system stores the particular logical block, to select a path to the identified storage node, and to send the input-output operation to the identified storage node over the selected path.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: November 28, 2023
    Assignee: Dell Products L.P.
    Inventors: Sanjib Mallick, Kurumurthy Gokam, Mohammad Salim Akhtar
  • Patent number: 11822706
    Abstract: An apparatus in one embodiment comprises at least one processing device comprising a processor coupled to a memory. The at least one processing device is configured to receive in a storage system, from a host device, an identifier of an encryption-enabled logical storage device of the storage system, to utilize the identifier to obtain in the storage system a device-specific key from a key management server external to the storage system, and to utilize the obtained device-specific key to process input-output operations directed to the encryption-enabled logical storage device from the host device. The host device in some embodiments comprises at least one virtual machine and the encryption-enabled logical storage device comprises a virtual storage volume of the at least one virtual machine. Metadata associated with the virtual storage volume illustratively comprises an encryption status indicator specifying whether or not encryption is enabled for the virtual storage volume.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: November 21, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Amit Pundalik Anchi, Sanjib Mallick
  • Patent number: 11816139
    Abstract: Methods, apparatus, and processor-readable storage media for block-level classification of unstructured data are provided herein. An example apparatus includes a host device comprising a processor coupled to memory, the host device being configured to communicate over a network with a storage system, and further being configured to: obtain a pointer to a page cache associated with an input-output operation for at least one page of unstructured data of a file; obtain an index node object of the file based at least in part on the pointer to the page cache; derive at least one characteristic of the file based at least in part on the obtained index node object; and provide an indication of the at least one characteristic to the storage system. The storage system determines whether to apply one or more functions to the unstructured data based on the indication.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: November 14, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Sanjib Mallick, Kundan Kumar, Sumana Ramachandra
  • Publication number: 20230351013
    Abstract: An apparatus comprises at least one processing device configured to implement a multi-path layer in a host device, wherein the multi-path layer controls delivery of input-output (IO) operations from the host device to a storage system over selected ones of a plurality of paths through a network. The multi-path layer is configured, for each of at least a subset of the IO operations, to store at least a process identifier, a user identifier and an access type for the IO operation. The multi-path layer is further configured to perform analytics on the stored process identifiers, user identifiers and access types to detect an access pattern, and responsive to the detected access pattern having one or more designated characteristics associated with malware, to generate an alert. The alert may be generated by inserting security alert indicators into respective ones of the IO operations, for extraction therefrom by the storage system.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 2, 2023
    Inventors: Sanjib Mallick, Arieh Don, Elik Levin, Kundan Kumar, Gaurav Singh
  • Patent number: 11789624
    Abstract: An apparatus comprises at least one processing device that includes a processor coupled to a memory. The processing device is configured to control delivery of input-output operations from a host device to at least first and second storage systems over selected ones of a plurality of paths through a network, to detect a single point of failure condition relating to a given one of the paths to a particular logical storage device in one of the first and second storage systems, and to determine whether or not the particular logical storage device is accessible in another one of the first and second storage systems. Different types of notifications are generated by the processing device depending on whether or not the particular logical storage device is accessible in the other one of the first and second storage systems.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: October 17, 2023
    Assignee: Dell Products L.P.
    Inventors: Vinay G. Rao, Sanjib Mallick, Arieh Don
  • Publication number: 20230315291
    Abstract: An apparatus comprises a processing device configured to detect an input-output (IO) pressure condition relating to at least one logical storage volume of a storage system, to receive IO operations directed to the at least one logical storage volume, to extract processing entity identifiers from respective ones of the received IO operations, and to perform IO throttling for the at least one logical storage volume based at least in part on the extracted processing entity identifiers. For example, a first group of one or more of the IO operations each having a first processing entity identifier may be subject to the IO throttling, while a second group of one or more of the IO operations each having a second processing entity identifier different than the first processing entity identifier is not subject to the IO throttling. Other differences in IO throttling can be implemented using the extracted processing entity identifiers.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Inventors: Sanjib Mallick, Vinay G Rao, Arieh Don
  • Publication number: 20230297238
    Abstract: An apparatus includes at least one processing device configured to obtain information characterizing which of a plurality of storage nodes of a distributed storage system stores respective ones of a plurality of different logical blocks of a logical storage volume of the distributed storage system. The at least one processing device is further configured, for each of a plurality of input-output operations directed to a particular one of the logical blocks of the logical storage volume, to identify, based at least in part on the obtained information, which of the plurality of storage nodes of the distributed storage system stores the particular logical block, to select a path to the identified storage node, and to send the input-output operation to the identified storage node over the selected path.
    Type: Application
    Filed: March 16, 2022
    Publication date: September 21, 2023
    Inventors: Sanjib Mallick, Kurumurthy Gokam, Mohammad Salim Akhtar
  • Patent number: 11762588
    Abstract: An apparatus comprises at least one processing device. The at least one processing device is configured to obtain storage-side performance information maintained by a storage system in conjunction with processing of input-output operations directed to the storage system by a host device over a network, to dynamically select a particular one of a plurality of distinct load balancing policies available in the host device based at least in part on the obtained storage-side performance information, and to apply the selected load balancing policy in directing additional input-output operations from the host device to the storage system. At least one of the load balancing policies comprises a storage cache aware load balancing policy that causes different ones of the input-output operations to be directed to different cache entities of the storage system based at least in part on cache-related performance metrics of the obtained storage-side performance information.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: September 19, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Amit Pundalik Anchi, Rimpesh Patel, Sanjib Mallick
  • Patent number: 11755222
    Abstract: An apparatus comprises a processing device configured to control delivery of input-output operations from a host device to a storage system over selected ones of a plurality of paths through a network. The processing device is further configured to identify whether operational information of the host device corresponding to a given write input-output operation comprises one or more index nodes, and to analyze the one or more index nodes responsive to a positive identification. The processing device is also configured to determine whether one or more portions of data corresponding to the given write input-output operation comprise file data based on the analysis of the one or more index nodes, to encrypt at least part of the file data responsive to an affirmative determination, and to deliver the given write input-output operation comprising the encrypted file data to the storage system.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: September 12, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Kundan Kumar, Sanjib Mallick
  • Patent number: 11722564
    Abstract: A multi-path input-output (MPIO) driver in a host server reduces host-copy migration data transmission rate based on decrease in foreground IO response time. A baseline foreground IO response time measured before commencement of the host-copy migration is compared with a reference foreground IO response time measured after commencement of the host-copy migration. Increase in the foreground IO response time, expressed as a percentage or time value, that satisfies a predetermined limit will trigger reduction of the host-copy migration data transmission rate. The reference foreground IO response time is repeatedly measured and updated each time the host-copy migration data transmission rate is decreased.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: August 8, 2023
    Assignee: DELL PRODUCTS L.P.
    Inventors: Arieh Don, Sanjib Mallick, Vinay Rao, Drew Tonnesen
  • Publication number: 20230185467
    Abstract: An apparatus comprises a processing device that includes a processor coupled to a memory. The processing device is configured to identify a source multi-path device in first multi-pathing software, to create a target multi-path device in second multi-pathing software different than the first multi-pathing software, to copy a set of paths of the source multi-path device to the target multi-path device, to add to the set of paths of the source multi-path device a new path to the target multi-path device, and to remove paths other than the new path from the source multi-path device. Such an arrangement illustratively provides non-disruptive switching of path selection functionality of a host device from the source multi-path device of the first multi-pathing software to the target multi-path device of the second multi-pathing software. The source and target multi-path devices illustratively utilize different storage access protocols, such as respective SCSI and NVMe access protocols.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 15, 2023
    Inventors: Sanjib Mallick, Kurumurthy Gokam, Mohammad Salim Akhtar