Abstract: An over-voltage protection circuit suitable for use at a front-end of an on-chip analog module such as an analog-to-digital converter (ADC) includes an input potential divider that can be disconnected from the module when the module is idle (or working on any other input such as the ADC sampling another channel causing the current channel to be idle) while still providing protection for front-end devices. A first NMOS transistor pair connects or disconnects the potential divider to or from ground in response to a control signal, and a second transistor pair including a NMOS transistor and a PMOS transistor ensures that the output does not rise above the supply voltage.

Abstract: An over-voltage protection circuit suitable for use at a front-end of an on-chip analog module such as an analog-to-digital converter (ADC) includes an input potential divider that can be disconnected from the module when the module is idle (or working on any other input such as the ADC sampling another channel causing the current channel to be idle) while still providing protection for front-end devices. A first NMOS transistor pair connects or disconnects the potential divider to or from ground in response to a control signal, and a second transistor pair including a NMOS transistor and a PMOS transistor ensures that the output does not rise above the supply voltage.

Abstract: An input control circuit that can be used to drive analog switches of analog modules such as an analog-to-digital converter (ADC) enables a sampling switch to receive a higher input voltage than the voltage rating of the devices comprising the sampling switch without risk of damage and without the need for a resistor divider network. The input control circuit and switch both receive an input voltage to be processed and the input control circuit generates a control signal for the switch that is derived from a pre-charged capacitor. The control circuit permits the design and manufacture of high voltage analog modules using low voltage devices, which can save on mask costs without any performance trade-offs.

Abstract: A charge pump circuit includes a delay circuit, a transistor, and a capacitor. The charge pump receives an input signal and outputs an output signal. The delay circuit receives a first signal based on the input signal and outputs a first delayed signal. The transistor includes a gate, a first channel node, and a second channel node. The first channel node receives the first signal. The second channel node is connected to the output and to a first plate of the capacitor. A second plate of the capacitor receives a second signal based on the first delayed signal. The charge pump circuit is adapted to operate such that the voltage range of the output signal is greater than the voltage range of the input signal.

Abstract: A programmable gain amplifier (PGA) includes an op amp, an input circuit, a feedback circuit, and a calibration circuit. The input circuit is connected between a PGA input node and an op-amp input node and selectively applies the analog input signal to the op-amp input node. The feedback circuit is connected between an op-amp output node and the op-amp input node and applies the amplified analog output signal as a feedback signal to the op-amp input node. The calibration circuit is connected between a calibration reference node and the op-amp input node and selectively connects the calibration reference node directly to the op-amp input node without traversing any of the input circuit. The PGA may be implemented as a single-ended or differential amplifier. The PGA avoids reduced linearity resulting from series combinations of switches in the input circuit when configured for its normal operating mode.

Abstract: A SAR ADC includes capacitors, a comparator, and a SAR logic circuit. The capacitors include a first set of capacitors and an error-detection capacitor. The first set of capacitors generates a first set of voltage signals that are compared with a common-mode voltage signal (VCM) by the comparator during a first set of comparison cycles. The comparator generates a first set of control signals that is used by the SAR logic circuit to successively approximate the first set of voltage signals and generate a first set of bits. An error-detection capacitor generates an error-detection signal that is compared with the common-mode voltage signal VCM by the comparator to generate an error-detection control signal. The SAR logic circuit compensate for an error in the first set of bits based the logic state of the error-detection control signal.

Abstract: A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.

Abstract: A programmable gain amplifier (PGA) includes an op amp, an input circuit, a feedback circuit, and a calibration circuit. The input circuit is connected between a PGA input node and an op-amp input node and selectively applies the analog input signal to the op-amp input node. The feedback circuit is connected between an op-amp output node and the op-amp input node and applies the amplified analog output signal as a feedback signal to the op-amp input node. The calibration circuit is connected between a calibration reference node and the op-amp input node and selectively connects the calibration reference node directly to the op-amp input node without traversing any of the input circuit. The PGA may be implemented as a single-ended or differential amplifier. The PGA avoids reduced linearity resulting from series combinations of switches in the input circuit when configured for its normal operating mode.

Abstract: A data acquisition system for converting an analog input signal to a digital output signal includes a programmable gain amplifier (PGA), an analog to digital converter (ADC), and an averaging module. The PGA generates first and second amplified signals during respective first and second conversion cycles. The first and second amplified signals include respective first and second amplified input signals and first and second sets of offset and noise signals. The first and second amplified input signals have the same polarities, and the first and second sets of offset and noise signals have opposite polarities. The ADC generates first and second digital samples corresponding to the first and second amplified signals respectively and the averaging module averages the first and second digital samples to eliminate the first and second sets of offset and noise signals from the digital output signal.

Abstract: A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.

Abstract: A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.

Abstract: A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.