Abstract: A three-dimensional (3D) NAND memory structure may include alternating layers of materials arranged in a vertical stack on a silicon substrate, such as alternating oxide and nitride layers. The alternating nitride layers may later be removed, and the recesses may be filled with a conductive material to form word lines for the memory array. To avoid pinching off these recesses with silicon byproducts from a traditional wet etch, a dry etch may be instead be used to remove the nitrite layers. To protect the silicon substrate, a first insulating layer may be deposited at the bottom of the slit to cover the exposed silicon substrate before performing the dry etch. After applying a second insulating layer to cover the alternating oxide/nitride layers, a directional etch may punch through both insulating layers to again expose the silicon substrate before applying a solid material fill in the slit.

Abstract: A method for forming a nanosheet device. The method may include providing a heterostructure device stack above a semiconductor substrate. The method may include patterning the heterostructure device stack to define a dummy gate region, and before forming a source drain recess adjacent the dummy gate region, selectively removing a first set of sacrificial layers of the heterostructure device stack within the dummy gate region.

Abstract: Processing methods may be performed to form an airgap spacer on a semiconductor substrate. The methods may include forming a spacer structure including a first material and a second material different from the first material. The methods may include forming a source/drain structure. The source/drain structure may be offset from the second material of the spacer structure by at least one other material. The methods may also include etching the second material from the spacer structure to form the airgap. The source/drain structure may be unexposed to etchant materials during the etching.

Abstract: Embodiments of this disclosure relate to methods for removing a dummy material from under a superlattice structure. In some embodiments, after removing the dummy material, it is replaced with a bottom dielectric isolation layer beneath the superlattice structure.

Abstract: Methods of forming a nanosheet field effect transistor (FET) device with reduced source/drain contact resistance are provided herein. In some embodiments, a method of forming an FET device includes: etching a nanosheet stack of the nanosheet FET device to form a plurality of first source/drain regions and a plurality of second source/drain regions, the nanosheet stack comprising alternating layers of nanosheet channel layers and sacrificial nanosheet layers; depositing a silicide layer in the plurality of first source/drain regions at ends of the nanosheet channel layers via a selective silicidation process to control a length of the nanosheet channel layers between the first source/drain regions; and performing a metal fill process to fill the plurality of first source/drain regions, wherein the metal fill extends from a lowermost nanosheet channel layer to above an uppermost nanosheet channel layer to facilitate the reduced source/drain contact resistance.

Abstract: Processing methods may be performed to form an airgap spacer on a semiconductor substrate. The methods may include forming a spacer structure including a first material and a second material different from the first material. The methods may include forming a source/drain structure. The source/drain structure may be offset from the second material of the spacer structure by at least one other material. The methods may also include etching the second material from the spacer structure to form the airgap. The source/drain structure may be unexposed to etchant materials during the etching.

Abstract: Processing methods may be performed to form an airgap spacer on a semiconductor substrate. The methods may include forming a spacer structure including a first material and a second material different from the first material. The methods may include forming a source/drain structure. The source/drain structure may be offset from the second material of the spacer structure by at least one other material. The methods may also include etching the second material from the spacer structure to form the airgap. The source/drain structure may be unexposed to etchant materials during the etching.

Abstract: Processing methods may be performed to expose a contact region on a semiconductor substrate. The methods may include selectively removing a first region of a silicon material between source/drain regions of a semiconductor substrate to expose a first region of oxide material. The methods may include forming a liner over the first region of oxide material and contacting second regions of the silicon material proximate the source/drain regions of the semiconductor substrate. The methods may also include selectively removing the second regions of the silicon material proximate the source/drain regions of the semiconductor substrate to expose a second region of the oxide material. The methods may further include selectively removing the second region of the oxide material from a surface of a contact in the semiconductor structure.

Abstract: Processing methods may be performed to expose a contact region on a semiconductor substrate. The methods may include selectively removing a first region of a silicon material between source/drain regions of a semiconductor substrate to expose a first region of oxide material. The methods may include forming a liner over the first region of oxide material and contacting second regions of the silicon material proximate the source/drain regions of the semiconductor substrate. The methods may also include selectively removing the second regions of the silicon material proximate the source/drain regions of the semiconductor substrate to expose a second region of the oxide material. The methods may further include selectively removing the second region of the oxide material from a surface of a contact in the semiconductor structure.

Abstract: Embodiments described herein generally relate to forming a semiconductor structure. In one embodiment, a method of forming a semiconductor structure is formed herein. The method includes exposing an oxide layer of the semiconductor structure, depositing a polysilicon layer on the semiconductor structure, filling a first gap formed by exposing the oxide layer, depositing a hard mask on the polysilicon layer, selectively removing the hard mask and the polysilicon layer, depositing an oxide layer on the semiconductor structure, filling a second gap formed by selectively removing the hard mask and polysilicon layer, exposing the polysilicon layer deposited on the semiconductor structure, selectively removing the polysilicon layer from the first gap, and selectively removing an etch stop layer from a surface of a contact in the semiconductor structure.