Abstract: A circuit includes a sense amplifier, a first clamping circuit, a second clamping circuit, and a feedback circuit. The first clamping circuit includes first clamping branches coupled in parallel between the sense amplifier and a memory array. The second clamping circuit includes second clamping branches coupled in parallel between the sense amplifier and a reference array. The feedback circuit is configured to selectively enable or disable one or more of the first clamping branches or one or more of the second clamping branches in response to an output data outputted by the sense amplifier.

Abstract: The disclosure introduces a shift register is configured to enter a low power mode by disabling a portion of flip-flops (FFs) that handles upper bits of input data. The shift register includes first FF(s), second FF(s) and gating circuit. The first flip-flop (FF), includes input terminal coupled to first portion of input data. The second FF includes input terminal coupled to second portion of input data, an output terminal, a clock terminal coupled to a clock signal, a power terminal coupled to a supply power. The second portion of the input data is subsequent to the first portion of the input data. The gating circuit is coupled to the output terminal of the first FF, and configured to disable the second FF for storing the second portion of a subsequent input data according to output data currently being stored in the first FF.

Abstract: A computing circuit is provided. The computing circuit is disposed in a memory device and electrically coupled to a memory cell of the memory device. The computing circuit includes a weight decoder, a multiplier, an adder tree, and an accumulator. The weight decoder is configured to obtain a compressed weight from the memory cell and generate a decoded weight based on the compressed weight. The multiplier is configured to generate a partial-product by multiplying an input signal with the decoded weight. The adder tree is configured to generate a partial-sum by performing an addition operation based on the partial-product. The accumulator is configured to generate an accumulated sum by performing an accumulation operation based on the partial-sum and output an output signal based on the accumulated sum. The accumulated sum is left shifted based on a shift signal.

Abstract: A memory device includes a memory array, a multiply-accumulate (MAC) circuit and an encoder-decoder circuit. The MAC circuit performs a MAC operation on an encoded weight data stored in the memory array and an input data to generate a partial MAC result. An encoder of the encoder-decoder circuit is configured to encode m weight bits among n weight bits of weight data according to an encryption key to generate the encoded weight data, wherein m and n are positive integers, and m is less than n. A decoder of the encoder-decoder circuit is configured to detect an error in the partial MAC result according to the encryption key to generate a decoded partial MAC result.

Abstract: An Input/Output (I/O) circuit for a memory device is provided. The I/O circuit includes a charge integration circuit coupled to a bitline of the memory device. The charge integration circuit provides a sensing voltage based on a decrease of a voltage on the bitline. A comparator is coupled to the charge integration circuit. The comparator compares the sensing voltage with a reference voltage and provides an output voltage based on the comparison. A time-to-digital converter coupled to the comparator. The time-to-digital convertor converts a time associated with the output voltage to a digital value.

Abstract: A circuit includes a reference voltage node, first and second data lines, a sense amplifier, first and second switching devices coupled between the first and second data lines and first and second input terminals of the sense amplifier, third and fourth switching devices coupled between the first and second data lined and first and second nodes, fifth and sixth switching devices coupled between the first and second nodes and the reference voltage node, and first and second capacitive devices coupled between the first and second nodes and second and first input terminals. Each of the first through fourth switching devices is switched on and each of the fifth and sixth switching devices is switched off in a first operational mode, and each of the first through fourth switching devices is switched off and each of the fifth and sixth switching devices is switched on in a second operational mode.

Abstract: A gas treatment method, including: treating an exhaust gas discharged from a semiconductor process chamber using a gas treatment system; and discharging the treated exhaust gas, wherein the treating of the exhaust gas includes: operating a first thermal oxidizer to treat the exhaust gas discharged from the semiconductor process chamber, the first thermal oxidizer being connected to the semiconductor process chamber and allowing the treated exhaust gas to pass through a plasma processing apparatus connected to the first thermal oxidizer; stopping the operation of the first thermal oxidizer to perform maintenance on the first thermal oxidizer; and wherein the stopping the operation of the first thermal oxidizer comprises: performing maintenance on the first thermal oxidizer; and operating the plasma processing apparatus to treat the exhaust gas discharged from the semiconductor process chamber

Abstract: A computation apparatus and a computation method with input swapping are provided. The computation apparatus includes a non-zero detection circuit, a swapper policy circuit, a swapper matrix circuit, and an adder tree. The non-zero detection circuit is configured to receive input vectors, inspect non-zero operands in the input vectors and generate a non-zero indicative signal indicating the non-zero operands. The swapper policy circuit is configured to receive and interpret the non-zero indicative signal, and generate multiplexer (MUX) selection signals for swapping the non-zero operands according to a set of swapping policies. The swapper matrix circuit is configured to receive the input vectors and the MUX selection signal, and perform swapping on operands in the input vectors according to the MUX selection signal. The adder tree is configured to receive the input vectors with the swapped operands and perform additions on the input vectors to output a computation result.

Abstract: A memory test circuit is provided. The memory test circuit is disposed in a memory chip and electrically coupled to a memory macro of the memory chip. A high speed clock receives an input signal and an external clock signal. The input signal includes a plurality of test bits. A finite state machine controller provides a pattern type. A pattern generator generates and provides a test signal to at least one memory cell of the memory chip to write the test signal to the at least one memory cell based on the pattern type and the external clock signal. A test frequency of the test signal is determined based on the high speed clock. An output comparator outputs a comparison signal based on a difference between the test signal and a readout signal corresponding to the test signal read from the at least one memory cell.

Abstract: A memory test circuit is provided. The memory test circuit is disposed in a memory array and including: a test array, including test cells out of memory cells of the memory array; a write multiplexer, configured to selectively output one of a test signal and a reference voltage based on a write measurement signal, wherein the test signal is output to write into at least one test cell and the reference voltage is output to a sense amplifier; and a read multiplexer, configured to selectively receive and output one of a readout signal corresponding to the test signal and an amplified signal based on a read measurement signal, wherein the readout signal is read from the at least one test cell and the amplified signal is obtained for a read margin evaluation from the sense amplifier by amplifying a voltage difference between the readout signal and the reference voltage.

Abstract: An electrical connector assembly includes: a bracket; and at least one transmission assembly mounted to the bracket and including an internal printed circuit board (PCB), a board-mount connector connected to a first row of conductive pads disposed at a bottom end portion of the PCB, and a plug-in connector connected to a second row of conductive pads disposed at a front end portion of the PCB, wherein the PCB has a third row of conductive pads disposed at a rear end portion thereof.

Abstract: A circuit includes a sense amplifier, a first clamping circuit, a second clamping circuit, and a feedback circuit. The first clamping circuit includes first clamping branches coupled in parallel between the sense amplifier and a memory array. The second clamping circuit includes second clamping branches coupled in parallel between the sense amplifier and a reference array. The feedback circuit is configured to selectively enable or disable one or more of the first clamping branches or one or more of the second clamping branches in response to an output data outputted by the sense amplifier.

Abstract: A gas treatment system includes a first scrubber configured to treat a gas exhausted from a process chamber, a catalytic reactor connected to the first scrubber and configured to treat a gas passing through the first scrubber, and a second scrubber connected to the catalytic reactor and configured to treat a gas passing through the catalytic reactor, where the catalytic reactor includes a fluidized bed reactor (FBR).

Abstract: A robotic tool changer for machining center includes a drive mechanism, a first motor, and a rotary seat which are mounted on a body. The drive mechanism includes a first rotating shaft, a second rotating shaft, a first swing arm, a second swing arm, and a linkage member. The first rotating shaft and the second rotating shaft are arranged in parallel. The first swing arm is connected to the first rotating shaft while the second swing arm is connected to the second rotating shaft. Two ends of the linkage member are pivotally connected to the first swing arm and the second swing arm respectively. An end of the second rotating shaft is fixed to the rotary seat. Thereby, when the first motor drives the first rotating shaft to rotate, the rotary seat is driven to turn over.

Abstract: The present disclosure relates to a catalyst for preparing 1,2-pentanediol from furfural and/or furfuryl alcohol, and more particularly to a catalyst, which is configured such that a catalytically active metal containing both at least one transition metal and tin (Sn) is supported on a basic support and is capable of increasing reaction selectivity for 1,2-pentanediol, and a method of preparing 1,2-pentanediol using the same.

Abstract: A robotic tool changer for machining center includes a drive mechanism, a first motor, and a rotary seat which are mounted on a body. The drive mechanism includes a first rotating shaft, a second rotating shaft, a first swing arm, a second swing arm, and a linkage member. The first rotating shaft and the second rotating shaft are arranged in parallel. The first swing arm is connected to the first rotating shaft while the second swing arm is connected to the second rotating shaft. Two ends of the linkage member are pivotally connected to the first swing arm and the second swing arm respectively. An end of the second rotating shaft is fixed to the rotary seat. Thereby, when the first motor drives the first rotating shaft to rotate, the rotary seat is driven to turn over.

Abstract: A gas treatment system includes a first scrubber, a regenerative catalytic oxidizer (RCO) that treats gas that passes through the first scrubber, a second scrubber that treats the gas that passed through the regenerative catalytic oxidizer, and a dielectric barrier discharge (DBD) plasma reactor that treats the gas that passed through the second scrubber. The regenerative catalytic oxidizer includes a two-bed regenerative catalytic reactor.

Abstract: Systems, methods, and non-transitory computer-readable storage media for detecting a wearing status of a wearable device, the wearing status indicating whether a user is wearing the wearable device and sending wearing status data to a companion communication device to control a behavior of the companion communication device.

Abstract: Systems, methods, and non-transitory computer-readable storage media for detecting a wearing status of a wearable device, the wearing status indicating whether a user is wearing the wearable device and sending wearing status data to a companion communication device to control a behavior of the companion communication device.

Abstract: Systems, methods, and non-transitory computer-readable storage media for detecting a wearing status of a wearable device, the wearing status indicating whether a user is wearing the wearable device and sending wearing status data to a companion communication device to control a behavior of the companion communication device.