Abstract: A digital data processing arrangement for providing automatic substitution of a spare memory module for a malfunctioning portion of the system memory is disclosed. The substitution takes place in a manner transparent to the software programs being run in the processing system. The system memory is organized as a plurality of memory modules, each having an identical number of individually addressable words. A particular module is enabled on receipt of an appropriate signal via a dedicated lead from the system processor unit, while a particular word within that module is specified by an address received via an address bus running to address decoder units at all modules. When the error detection and identification routines of the system processor determine that a particular module is malfunctioning, a hardware register and accompanying comparison logic are arranged such that a spare module is accessed whenever the particular malfunctioning module is subsequently addressed.

Abstract: A virtual encoding scheme for use in random access memories is disclosed. Data errors, incorrect memory word access errors, and errors resulting from multiple memory word access are all detectable through use of the encoding scheme. The novel approach includes the generation of two distinct check code fields which are stored along with the data. A first check code field is generated as a function of the data and is capable of reflecting all unidirectional data failures. A second check code field is generated as a function of the address of the memory word containing the data and is capable of reflecting incorrect memory word access. The two check fields can be stored either in the same physical memory location as the data or in a supplementary memory at an address numerically identical to that at which the data is kept. During readout, the two check fields are regenerated and compared to those previously stored.