Patents by Inventor Sanu Mathew

Sanu Mathew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10599429
    Abstract: Disclosed embodiments relate to a variable format, variable sparsity matrix multiplication (VFVSMM) instruction. In one example, a processor includes fetch and decode circuitry to fetch and decode a VFVSMM instruction specifying locations of A, B, and C matrices having (M×K), (K×N), and (M×N) elements, respectively, execution circuitry, responsive to the decoded VFVSMM instruction, to: route each row of the specified A matrix, staggering subsequent rows, into corresponding rows of a (M×N) processing array, and route each column of the specified B matrix, staggering subsequent columns, into corresponding columns of the processing array, wherein each of the processing units is to generate K products of A-matrix elements and matching B-matrix elements having a same row address as a column address of the A-matrix element, and to accumulate each generated product with a corresponding C-matrix element.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: Mark A. Anders, Himanshu Kaul, Sanu Mathew
  • Publication number: 20190386815
    Abstract: Disclosed embodiments relate to a unified Advanced Encryption Standard (AES), SMS4, and Camellia (CML) accelerator. In one example, a processor includes fetch circuitry to fetch a cipher instruction specifying an opcode, a datum, and a key, the opcode to specify one of three cryptographic modes and an operation, decode circuitry to decode the fetched cipher instruction, and execution circuitry to respond to the decoded cipher instruction by performing the operation using a selected one of three block ciphers corresponding to the specified cryptographic mode and a unified cipher datapath shared by the three block ciphers, the unified cipher datapath comprising a plurality of hybrid substitution boxes (Sboxes) to perform Galois Field (GF) multiplications and inverse computations, wherein the unified cipher datapath is to implement an eighth-order polynomial isomorphically equivalent to each polynomial used by the three block ciphers by calculating and then combining two fourth-order polynomials.
    Type: Application
    Filed: June 15, 2018
    Publication date: December 19, 2019
    Inventors: Sudhir SATPATHY, Vikram SURESH, Sanu MATHEW
  • Publication number: 20190325166
    Abstract: Embodiments are directed to post quantum public key signature operation for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including a dedicated cryptographic hash hardware engine, and a reconfigurable fabric including logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device for public key signature operation, including mapping a state machine for public key generation and verification to the reconfigurable fabric, including mapping one or more cryptographic hash engines to the reconfigurable fabric, and combining the dedicated cryptographic hash hardware engine with the one or more mapped cryptographic hash engines for cryptographic signature generation and verification.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 24, 2019
    Applicant: Intel Corporation
    Inventors: Vikram Suresh, Sanu Mathew, Rafael Misoczki, Santosh Ghosh, Raghavan Kumar, Manoj Sastry, Andrew H. Reinders
  • Publication number: 20190319782
    Abstract: In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 17, 2019
    Applicant: Intel Corporation
    Inventors: SANTOSH GHOSH, Vikram Suresh, Sanu Mathew, Manoj Sastry, Andrew H. Reinders, Raghavan Kumar, Rafael Misoczki
  • Publication number: 20190319797
    Abstract: In one example an apparatus comprises a computer readable memory, hash logic to generate a message hash value based on an input message, signature logic to generate a signature to be transmitted in association with the message, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key, and accelerator logic to pre-compute at least one set of inputs to the signature logic. Other examples may be described.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 17, 2019
    Applicant: Intel Corporation
    Inventors: VIKRAM SURESH, SANU MATHEW, MANOJ SASTRY, SANTOSH GHOSH, RAGHAVAN KUMAR, RAFAEL MISOCZKI
  • Publication number: 20190319796
    Abstract: In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 17, 2019
    Applicant: Intel Corporation
    Inventors: SANTOSH GHOSH, Vikram Suresh, Sanu Mathew, Manoj Sastry, Andrew H. Reinders, Raghavan Kumar, Rafael Misoczki
  • Publication number: 20190319799
    Abstract: In one example an apparatus comprises a computer readable memory, a signature logic to generate a signature to be transmitted in association with a message, the signature logic to apply a hash-based signature scheme to the message using a private key to generate the signature comprising a public key, or a verification logic to verify a signature received in association with the message, the verification logic to apply the hash-based signature scheme to verify the signature using the public key, and an accelerator logic to apply a structured order to at least one set of inputs to the hash-based signature scheme. Other examples may be described.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 17, 2019
    Applicant: Intel Corporation
    Inventors: Vikram Suresh, Sanu Mathew, Manoj Sastry, Santosh Ghosh, Raghavan Kumar, Rafael Misoczki
  • Publication number: 20190319804
    Abstract: A mechanism is described for facilitating unified accelerator for classical and post-quantum digital signature schemes in computing environments, according to one embodiment. A method of embodiments, as described herein, includes unifying classical cryptography and post-quantum cryptography through a unified hardware accelerator hosted by a trusted platform of the computing device. The method may further include facilitating unification of a first finite state machine associated with the classical cryptography and a second finite state machine associated with the post-quantum cryptography though one or more of a single the hash engine, a set of register file banks, and a modular exponentiation engine.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 17, 2019
    Applicant: Intel Corporation
    Inventors: SANU MATHEW, MANOJ SASTRY, SANTOSH GHOSH, VIKRAM SURESH, ANDREW H. REINDERS, RAGHAVAN KUMAR, RAFAEL MISOCZKI
  • Publication number: 20190319803
    Abstract: In one example an apparatus comprises a computer-readable memory, signature logic to compute a message hash of an input message using a secure hash algorithm, process the message hash to generate an array of secret key components for the input message, apply a hash chain function to the array of secret key components to generate an array of signature components, the hash chain function comprising a series of even-index hash chains and a series of odd-index hash chains, wherein the even-index hash chains and the odd-index hash chains generate a plurality of intermediate node values and a one-time public key component between the secret key components and the signature components and store at least some of the intermediate node values in the computer-readable memory for use in one or more subsequent signature operations. Other examples may be described.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 17, 2019
    Applicant: Intel Corporation
    Inventors: RAFAEL MISOCZKI, VIKRAM SURESH, SANTOSH GHOSH, MANOJ SASTRY, SANU MATHEW, RAGHAVAN KUMAR
  • Publication number: 20190305970
    Abstract: An apparatus is provided which comprises: an entropy source to produce a first random sequence of bits, wherein the entropy source comprises an array of bi-stable cross-coupled inverter cells; a first circuitry coupled to the entropy source, wherein the first circuitry to generate an entropy source selection set; and a second circuitry coupled to the entropy source and the first circuitry, wherein the second circuitry is to receive the first random sequence and the entropy source selection set, and wherein the second circuitry is to generate a second random sequence.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Sudhir Satpathy, Vikram Suresh, Sanu Mathew
  • Patent number: 10374793
    Abstract: An instruction and logic for a Simon-based hashing for validation are described. In one embodiment, a processor comprises: a memory the memory to store a plurality of values; and a hash circuit comprising a Simon cipher circuit operable to receive the plurality of values from the memory, to apply a Simon cipher, and to generate an output for each of the plurality of values; and circuitry coupled to the Simon cipher circuit to combine outputs from the Simon cipher circuit for each value of the plurality of values into a hash digest that is indicative of whether the values in the memory are valid.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: August 6, 2019
    Assignee: INTEL CORPORATION
    Inventors: Himanshu Kaul, Sanu Mathew, Mark Anders, Jesse Walker, Jason Sandri
  • Patent number: 10346343
    Abstract: Encryption of a BIOS using a programmable logic device (PLD) is described. A PLD may include a static random-access memory area including programmable logic in a Lookup Table to receive a request to authenticate a basic input/output system (BIOS) executing on a processor coupled to the PLD. The PLD may calculate a hash value of a message associated with the BIOS using a Secure Hash Algorithm (SHA). The PLD may also include a random-access memory area including a first embedded random access memory block (EBR) to store a first portion of a 256-bit message digest associated with the message, a fifth portion of the 256-bit message digest, and second, third, fourth, sixth, seventh, and eighth EBRs to store second, third, fourth, sixth, seventh, and eighth portions of the 256-bit message digest, respectively.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Vikram Suresh, Sudhir Satpathy, Sanu Mathew, Neeraj Upasani
  • Publication number: 20190199517
    Abstract: An integrated circuit features technology for generating a keystream. The integrated circuit comprises a cipher block with a linear feedback shift register (LFSR) and a finite state machine (FSM). The LFSR and the FSM are configured to generate a stream of keys, based on an initialization value and an initialization key. The FSM comprises an Sbox that is configured to use a multiplicative mask to mask data that is processed by the Sbox when the LFSR and the FSM are generating the stream of keys. Other embodiments are described and claimed.
    Type: Application
    Filed: February 28, 2019
    Publication date: June 27, 2019
    Inventors: Sudhir Satpathy, Vikram Suresh, Sanu Mathew
  • Patent number: 10326596
    Abstract: Various embodiments are generally directed to techniques for secure message authentication and digital signatures, such as with a cipher-based hash function, for instance. Some embodiments are particularly directed to a secure authentication system that implements various aspects of the cipher-based hash function in dedicated hardware or circuitry. In various embodiments, the secure authentication system may implement one or more elements of the Whirlpool hash function in dedicated hardware. For instance, the compute-intensive substitute byte and mix rows blocks of the block cipher in the Whirlpool hash function may be implemented in dedicated hardware or circuitry using a combination of Galois Field arithmetic and fused scale/reduce circuits. In some embodiments, the microarchitecture of the secure authentication system may be implemented with delayed add key to limit the memory requirement to three sequential registers.
    Type: Grant
    Filed: October 1, 2016
    Date of Patent: June 18, 2019
    Assignee: INTEL CORPORATION
    Inventors: Vikram Suresh, Sudhir Satpathy, Sanu Mathew
  • Patent number: 10218497
    Abstract: A hybrid AES-SMS4 hardware accelerator is described. A System on Chip implementing a hybrid AES-SMS4 hardware accelerator may include a processor core and a single hardware accelerator coupled to the processor core, the single hardware accelerator to encrypt or decrypt data. The single hardware accelerator may include a first block cipher to encrypt or decrypt the data according to a first encryption algorithm and a second block cipher to encrypt or decrypt the data according to a second encryption algorithm. The accelerator may further include a combined substitution box (Sbox) coupled to the first block cipher and the second block cipher, the combined Sbox comprising logic to perform Galois Field (GF) multiplications and inverse computations, wherein the inverse computations are common to the first block cipher and the second block cipher.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: February 26, 2019
    Assignee: Intel Corporation
    Inventors: Vikram Suresh, Sudhir Satpathy, Sanu Mathew
  • Publication number: 20190044739
    Abstract: An embodiment of a semiconductor package apparatus may include technology to generate a first output from a physically unclonable function (PUF) based on a challenge, modify the challenge based on the first output, and generate a response based on the modified challenge. Some embodiments may additionally or alternatively include technology to change a read sequence of the PUF based on an output of the PUF. Some embodiments may additionally or alternatively include technology to vary a latency of a linear feedback shift register based on an output from the PUF. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: March 30, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Manoj Sachdev, Vikram Suresh, Sanu Mathew, Sudhir Satpathy
  • Publication number: 20190042249
    Abstract: Methods and apparatuses relating to high-performance authenticated encryption are described.
    Type: Application
    Filed: April 2, 2018
    Publication date: February 7, 2019
    Inventors: VIKRAM SURESH, SANU MATHEW, SUDHIR SATPATHY, VINODH GOPAL
  • Publication number: 20190044699
    Abstract: Methods and apparatus for a reconfigurable Galois Field (GF) Sbox unit for Camellia, AES, and SM4 hardware accelerator are described. In one embodiment, a modified Substitute box (Sbox) leverages a common field of GF to incorporate a multi-cipher mode of operation. The hybrid Sbox design can reduce area and/or energy consumption. Other embodiments are also described and claimed.
    Type: Application
    Filed: June 28, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Sudhir Satpathy, Sanu Mathew, Vikram Suresh
  • Publication number: 20190042250
    Abstract: Disclosed embodiments relate to a variable format, variable sparsity matrix multiplication (VFVSMM) instruction. In one example, a processor includes fetch and decode circuitry to fetch and decode a VFVSMM instruction specifying locations of A, B, and C matrices having (M×K), (K×N), and (M×N) elements, respectively, execution circuitry, responsive to the decoded VFVSMM instruction, to: route each row of the specified A matrix, staggering subsequent rows, into corresponding rows of a (M×N) processing array, and route each column of the specified B matrix, staggering subsequent columns, into corresponding columns of the processing array, wherein each of the processing units is to generate K products of A-matrix elements and matching B-matrix elements having a same row address as a column address of the A-matrix element, and to accumulate each generated product with a corresponding C-matrix element.
    Type: Application
    Filed: June 8, 2018
    Publication date: February 7, 2019
    Inventors: Mark A. Anders, Himanshu Kaul, Sanu Mathew
  • Publication number: 20180097630
    Abstract: Various embodiments are generally directed to techniques for secure message authentication and digital signatures, such as with a cipher-based hash function, for instance. Some embodiments are particularly directed to a secure authentication system that implements various aspects of the cipher-based hash function in dedicated hardware or circuitry. In various embodiments, the secure authentication system may implement one or more elements of the Whirlpool hash function in dedicated hardware. For instance, the compute-intensive substitute byte and mix rows blocks of the block cipher in the Whirlpool hash function may be implemented in dedicated hardware or circuitry using a combination of Galois Field arithmetic and fused scale/reduce circuits. In some embodiments, the microarchitecture of the secure authentication system may be implemented with delayed add key to limit the memory requirement to three sequential registers.
    Type: Application
    Filed: October 1, 2016
    Publication date: April 5, 2018
    Applicant: INTEL CORPORATION
    Inventors: VIKRAM SURESH, SUDHIR SATPATHY, SANU MATHEW