Patents by Inventor Saori Mitsunaga

Saori Mitsunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11132235
    Abstract: A data processing method of a distributed data processing system, in which the base server collects and standardizes data and generates base data by node cut processing, the central server collects the attribute information of the column of the base data from a plurality of base servers and the relationship between the integration source and the integration destination of the base data by the node cut processing of the base server as base column integrated information, a combination of an integration source and an integration destination capable of reducing the data amount as a result of an replacement for calculating a combination of an integration source and an integration destination capable of reducing the data amount by exchanging the integration source and the integration destination when data is combined, the combination is notified to the base server as an exchange instruction.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: September 28, 2021
    Assignee: HITACHI, LTD.
    Inventors: Yoshihisa Ida, Saori Mitsunaga, Tsukasa Hosoya, Atsuyoshi Morishima, Yoshiki Aoyama
  • Publication number: 20190042317
    Abstract: A data processing method of a distributed data processing system, in which the base server collects and standardizes data and generates base data by node cut processing, the central server collects the attribute information of the column of the base data from a plurality of base servers and the relationship between the integration source and the integration destination of the base data by the node cut processing of the base server as base column integrated information, a combination of an integration source and an integration destination capable of reducing the data amount as a result of an replacement for calculating a combination of an integration source and an integration destination capable of reducing the data amount by exchanging the integration source and the integration destination when data is combined, the combination is notified to the base server as an exchange instruction.
    Type: Application
    Filed: February 16, 2017
    Publication date: February 7, 2019
    Inventors: Yoshihisa IDA, Saori MITSUNAGA, Tsukasa HOSOYA, Atsuyoshi MORISHIMA, Yoshiki AOYAMA
  • Patent number: 6826585
    Abstract: In a simultaneous-linear-equations solving method of calculating the numerical solutions of simultaneous linear equations having a coefficient matrix, all the elements of coefficient matrix elements including zero elements and all the elements of right-side vector elements are stored into an array. Next, a non-zero-structure-specifying index table is created which indicates the row number of a terminal-end non-zero element in each column and the column number of a terminal-end non-zero element in each row within the array. Moreover, a decomposition processing is executed toward the elements existing within a range indicated by the created index table. Finally, a forward/backward substitution processing is executed toward the coefficient matrix elements subjected to the decomposition processing and the right-side vector elements stored into the array, thereby determining the numerical solutions.
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: November 30, 2004
    Assignee: Hitachi Software Engineering Co., Ltd.
    Inventors: Saori Mitsunaga, Shinichi Tanaka, Hiroki Kawamura
  • Patent number: 6438713
    Abstract: A debugger for support of the debugging of a program, an array data displaying method in the debugger, and a recording medium having an array data displaying program in the debugger are disclosed. A debugger system may be provided with a data save unit and a display control unit so that a command is issued to a source program at a breakpoint to save array data. Next, an instruction for display of the saved data is made to display the data on a display unit. Thereby, the contents of an array can be saved without changing a source and the saving and display of array data can be performed asynchronously. Also, the debugger system may be provided with an array construction control unit, a shared element control unit and a display element sampling unit so that an array distributed to a plurality of processes is constructed by the array construction unit and is displayed in the form of a graph with the trimming performed by the display element sampling unit down to the proper number of elements.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: August 20, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Keigo Taira, Kazunori Watanabe, Yoichi Irie, Tsuyoshi Endo, Kenya Aoyagi, Saori Mitsunaga
  • Publication number: 20020077789
    Abstract: In a simultaneous-linear-equations solving method of calculating the numerical solutions of simultaneous linear equations having a coefficient matrix, all the elements of coefficient matrix elements including zero elements and all the elements of right-side vector elements are stored into an array. Next, a non-zero-structure-specifying index table is created which indicates the row number of a terminal-end non-zero element in each column and the column number of a terminal-end non-zero element in each row within the array. Moreover, a decomposition processing is executed toward the elements existing within a range indicated by the created index table. Finally, a forward/backward substitution processing is executed toward the coefficient matrix elements subjected to the decomposition processing and the right-side vector elements stored into the array, thereby determining the numerical solutions.
    Type: Application
    Filed: October 19, 2001
    Publication date: June 20, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Saori Mitsunaga, Schinichi Tanaka, Hiroki Kawamura
  • Patent number: 6389439
    Abstract: A different phase type is specified toward each of a plurality of processors constituting a parallel computer, thereby, in a changeable manner, generating M sequence random numbers having the phase type. An information inputting unit inputs, into a random-number generating process unit, the number of the processors used in a parallel processing, the number of the random numbers to be generated by a single processor, the number of the phase types of the random numbers to be generated, and phase type information for each processor. The random-number generating process unit includes a phase-type management-table creating process unit, an initial-value table generating process unit, and a random-number generating calculation unit.
    Type: Grant
    Filed: July 14, 1999
    Date of Patent: May 14, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Saori Mitsunaga, Nobuhiro Ioki