Patents by Inventor Sarath C. Puthenthermadam

Sarath C. Puthenthermadam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Endurance of silicon-oxide-nitride-oxide-silicon (SONOS) memory cells
    Patent number: 9378821
    Abstract: Apparatuses and methods of pulse shaping a pulse signal for programming and erasing a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory cell are described. In one method a pulse shape of a pulse signal is controlled to include four or more phases for programming or erasing a SONOS memory cell. A write cycle is performed to program or erase the SONOS memory with the pulse signal with the four or more phases.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: June 28, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Venkatraman Prabhakar, Long Hinh, Kaveh Shakeri, Sarath C. Puthenthermadam
  • Nonvolatile memory cells and methods of making such cells
    Patent number: 8897067
    Abstract: A memory cell can include at least a first programmable section coupled between a supply node and a first data node; a volatile storage circuit coupled to the first data node; and the programmable section includes a programmable transistor having a first source/drain (S/D) region shared with a first transistor, and a second S/D region shared with a second transistor; wherein the first S/D region has a different dopant diffusion profile than the second S/D region, and the programmable transistor has a charge storage structure formed between its control gate and its channel. Methods of forming such a memory cell are also disclosed.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: November 25, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Venkatraman Prabhakar, Kaveh Shakeri, Long T Hinh, Sarath C. Puthenthermadam
  • NONVOLATILE MEMORY CELLS AND METHODS OF MAKING SUCH CELLS
    Publication number: 20140264552
    Abstract: A memory cell can include at least a first programmable section coupled between a supply node and a first data node; a volatile storage circuit coupled to the first data node; and the programmable section includes a programmable transistor having a first source/drain (S/D) region shared with a first transistor, and a second S/D region shared with a second transistor; wherein the first S/D region has a different dopant diffusion profile than the second S/D region, and the programmable transistor has a charge storage structure formed between its control gate and its channel. Methods of forming such a memory cell are also disclosed.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 18, 2014
    Applicant: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Venkatraman Prabhakar, Kaveh Shakeri, Long Hinh, Sarath C. Puthenthermadam