Abstract: In a method and system for filtering an input signal with a filter included in a phase locked loop (PLL), a unidirectional feedback path is configured from an output of the filter to an input of the filter. The unidirectional feedback path includes a feedback resistor that is configured to adjust a bandwidth of the PLL. A zero path is configured from the output to a voltage reference, such as ground. The zero path includes a capacitor coupled in series with a bias resistor. The bias resistor, which along with the capacitor determines a zero frequency of the filter, is configured to reduce a value of the capacitor without a substantial increase in a phase noise of the PLL due to the unidirectional nature of the feedback. A reduction in the value of the capacitor enables a corresponding reduction in a silicon area to form the capacitor.

Abstract: In a method and system for filtering an input signal with a filter included in a phase locked loop (PLL), a unidirectional feedback path is configured from an output of the filter to an input of the filter. The unidirectional feedback path includes a feedback resistor that is configured to adjust a bandwidth of the PLL. A zero path is configured from the output to a voltage reference, such as ground. The zero path includes a capacitor coupled in series with a bias resistor. The bias resistor, which along with the capacitor determines a zero frequency of the filter, is configured to reduce a value of the capacitor without a substantial increase in a phase noise of the PLL due to the unidirectional nature of the feedback. A reduction in the value of the capacitor enables a corresponding reduction in a silicon area to form the capacitor.