Patents by Inventor Saravanan MARIMUTHU
Saravanan MARIMUTHU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11823962Abstract: Aspects of the disclosure are directed to sensing integrated circuit (IC) Back End Of Line (BEOL) process corners. In one aspect, an apparatus for sensing IC BEOL process corners includes a ring oscillator including a plurality of ring oscillator stages configured to generate an output waveform with a frequency state; and a shield net circuit including a plurality of shield net stages corresponding to the plurality of ring oscillator stages, the shield net circuit having a toggle input. And, a method includes generating an output waveform with a frequency state using a ring oscillator that includes a plurality of ring oscillator stages; modifying a plurality of ring oscillator stage time delays through a coupling between a plurality of shield net stages and the plurality of ring oscillator stages; and selecting the frequency state using a toggle input of a shield net circuit which includes the plurality of shield net stages.Type: GrantFiled: February 19, 2021Date of Patent: November 21, 2023Assignee: QUALCOMM INCORPORATEDInventors: Saravanan Marimuthu, De Lu, Baldeo Sharan Sharma, Peeyush Kumar Parkar, Venkat Narayanan, Rui Li, Samy Shafik Tawfik Zaynoun, Min Chen, David Kidd, Amit Patil
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Publication number: 20220270938Abstract: Aspects of the disclosure are directed to sensing integrated circuit (IC) Back End Of Line (BEOL) process corners. In one aspect, an apparatus for sensing IC BEOL process corners includes a ring oscillator including a plurality of ring oscillator stages configured to generate an output waveform with a frequency state; and a shield net circuit including a plurality of shield net stages corresponding to the plurality of ring oscillator stages, the shield net circuit having a toggle input. And, a method includes generating an output waveform with a frequency state using a ring oscillator that includes a plurality of ring oscillator stages; modifying a plurality of ring oscillator stage time delays through a coupling between a plurality of shield net stages and the plurality of ring oscillator stages; and selecting the frequency state using a toggle input of a shield net circuit which includes the plurality of shield net stages.Type: ApplicationFiled: February 19, 2021Publication date: August 25, 2022Inventors: Saravanan MARIMUTHU, De LU, Baldeo Sharan SHARMA, Peeyush Kumar PARKAR, Venkat NARAYANAN, Rui LI, Samy Shafik Tawfik ZAYNOUN, Min CHEN, David KIDD, Amit PATIL
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Patent number: 10533283Abstract: Described herein are devices and methods for the drying of permeable and semi-permeable webs such as paper products in a physical environment with limited space while providing for higher flow rates. The devices and methods of the present invention are for use with rotating, foraminous shelled roll dryers and are implemented by redesigning the aspects of the devices and methods associated with exhausting spent drying gas.Type: GrantFiled: July 18, 2017Date of Patent: January 14, 2020Assignee: Valmet, Inc.Inventors: Richard Alan Parker, Laurent R. Parent, Saravanan Marimuthu
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Publication number: 20190024313Abstract: Described herein are devices and methods for the drying of permeable and semi-permeable webs such as paper products in a physical environment with limited space while providing for higher flow rates. The devices and methods of the present invention are for use with rotating, foraminous shelled roll dryers and are implemented by redesigning the aspects of the devices and methods associated with exhausting spent drying gas.Type: ApplicationFiled: July 18, 2017Publication date: January 24, 2019Inventors: Richard Alan Parker, Laurent R. Parent, Saravanan Marimuthu
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Patent number: 9053773Abstract: An integrated circuit element is disclosed having a memory device; a P-type semiconductor region including a first semiconductor device from a first memory port circuit coupled to the memory device and configured to enable access to the memory device when the first semiconductor device is activated; an N-type semiconductor region including a second semiconductor device from a second memory port circuit coupled to the memory device and configured to enable access to the memory device when the second semiconductor device is activated; and a plurality of signal lines distributed over the P-type and N-type semiconductor regions including a first memory port selection line coupled to allow the first semiconductor device to be activated; a second memory port selection line coupled to allow the second semiconductor device to be activated; and a clock signal line placed between the first memory port selection line and the second memory port selection line.Type: GrantFiled: September 12, 2013Date of Patent: June 9, 2015Assignee: QUALCOMM IncorporatedInventors: Saravanan Marimuthu, Sachin Bapat, Sakthivel Packirisamy
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Patent number: 9020084Abstract: Techniques for resolving a metastable state in a synchronizer are described herein. In one embodiment, a circuit for resolving a metastable state in a synchronizer comprises a signal delay circuit coupled to a node of the synchronizer, wherein the signal delay circuit is configured to delay a data signal at the node to produce a delayed data signal, and a transmission circuit coupled to the signal delay circuit, wherein the transmission circuit is configured to couple the delayed data signal to the node after a delay from a first edge of a clock signal.Type: GrantFiled: January 31, 2013Date of Patent: April 28, 2015Assignee: QUALCOMM IncorporatedInventors: Seid Hadi Rasouli, Animesh Datta, Saravanan Marimuthu, Ohsang Kwon
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Publication number: 20150109025Abstract: A CMOS device includes a PMOS transistor and an NMOS transistor. The CMOS device further includes a poly interconnect connecting together a drain of the PMOS transistor and a drain of the NMOS transistor. The poly interconnect may be located on an edge of a standard cell including the device. The CMOS device may further include a first interconnect on an MD layer connecting the drain of the PMOS transistor to the poly interconnect, and a second interconnect on the MD layer connecting the drain of the NMOS transistor to the poly interconnect. The PMOS transistor and the NMOS transistor may operate as a CMOS inverter. The CMOS device may be a tristate inverter, and specifically, a tristate inverter within a latch array.Type: ApplicationFiled: October 18, 2013Publication date: April 23, 2015Applicant: Qualcomm IncorporatedInventors: Saravanan MARIMUTHU, Sakthivel PACKIRISAMY, Vijayalakshmi RANGANNA
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Publication number: 20140211893Abstract: Techniques for resolving a metastable state in a synchronizer are described herein. In one embodiment, a circuit for resolving a metastable state in a synchronizer comprises a signal delay circuit coupled to a node of the synchronizer, wherein the signal delay circuit is configured to delay a data signal at the node to produce a delayed data signal, and a transmission circuit coupled to the signal delay circuit, wherein the transmission circuit is configured to couple the delayed data signal to the node after a delay from a first edge of a clock signal.Type: ApplicationFiled: January 31, 2013Publication date: July 31, 2014Applicant: QUALCOMM IncorporatedInventors: Seid Hadi Rasouli, Animesh Datta, Saravanan Marimuthu, Ohsang Kwon
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Publication number: 20140177344Abstract: An integrated circuit element is disclosed having a memory device; a P-type semiconductor region including a first semiconductor device from a first memory port circuit coupled to the memory device and configured to enable access to the memory device when the first semiconductor device is activated; an N-type semiconductor region including a second semiconductor device from a second memory port circuit coupled to the memory device and configured to enable access to the memory device when the second semiconductor device is activated; and a plurality of signal lines distributed over the P-type and N-type semiconductor regions including a first memory port selection line coupled to allow the first semiconductor device to be activated; a second memory port selection line coupled to allow the second semiconductor device to be activated; and a clock signal line placed between the first memory port selection line and the second memory port selection line.Type: ApplicationFiled: September 12, 2013Publication date: June 26, 2014Applicant: QUALCOMM IncorporatedInventors: Saravanan MARIMUTHU, Sachin BAPAT, Sakthivel PACKIRISAMY