Patents by Inventor Sasa Ristic

Sasa Ristic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180081118
    Abstract: Two or more monolithic or heterogeneously integrated substrates are attached to each other and optically edge-coupled using spot-size converters. Spot-size converters are placed between planar optical waveguides and cleaved or etched facets in each substrate. The facets are provide optical edge coupling and the spot-size converters are used to adjust at least the size, shape, and divergence of the optical beams entering or exiting the optical waveguides as to improve the optical coupling between the substrates. In addition to spot-size converters, filtering and other light adjusting elements may be placed between the substrates. Integrated lasers, semiconductor optical amplifiers, and photonic integrated circuits can be provided with complementary metal-oxide semiconductor (CMOS)-compatible silicon (Si) photonic substrates, which can also contain integrated electronics.
    Type: Application
    Filed: May 1, 2017
    Publication date: March 22, 2018
    Applicant: Biond Photonics Inc.
    Inventors: Jonathan Klamkin, Sasa Ristic
  • Publication number: 20170207600
    Abstract: Methods for realizing integrated lasers and photonic integrated circuits on complimentary metal-oxide semiconductor (CMOS)-compatible silicon (Si) photonic chips, potentially containing integrated electronics, are disclosed. The integration techniques rely on light coupling with integrated light coupling elements such as turning mirrors, lenses, and surface grating couplers. Light is coupled from between two or more substrates using the light coupling elements. The technique can realize integrated lasers on Si where a gain flip chip (the second substrate) is bonded to a Si chip (the first substrate) and light is coupled between a waveguide in the gain flip chip to a Si waveguide by way of a turning mirror or grating coupler in the flip chip and a grating coupler in the Si chip. Integrated lenses and other elements such as spot-size converters can also be incorporated to alter the mode from the gain flip chip to enhance the coupling efficiency to the Si chip.
    Type: Application
    Filed: July 14, 2015
    Publication date: July 20, 2017
    Applicant: Biond Photonics Inc.
    Inventors: Jonathan Klamkin, Sasa Ristic
  • Patent number: 9423851
    Abstract: A power management integrated circuit comprises a plurality of power source circuits power received at a power supply input terminal to supply power to a plurality of power supply output terminals. A plurality of power source circuits is coupled between the power supply input terminal and the respective power supply output terminals. The power management integrated circuit comprises an active configuration memory and a communication interface with at least one terminal for uploading configuration data from outside the power management integrated circuit into the configuration memory. A control circuit controls operating parameters of respective ones of the power source circuits dependent on the configuration data from the active configuration memory. Thus, the power management integrated circuit is able to switch between different power supply states in a dynamically configurable way, without requiring external control over the configuration during switching.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: August 23, 2016
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Sasa Ristic, Insun Van Loo, Patrick E. G. Smeets
  • Publication number: 20150331469
    Abstract: A power management integrated circuit comprises a plurality of power source circuits power received at a power supply input terminal to supply power to a plurality of power supply output terminals. A plurality of power source circuits is coupled between the power supply input terminal and the respective power supply output terminals. The power management integrated circuit comprises an active configuration memory and a communication interface with at least one terminal for uploading configuration data from outside the power management integrated circuit into the configuration memory. A control circuit controls operating parameters of respective ones of the power source circuits dependent on the configuration data from the active configuration memory. Thus, the power management integrated circuit is able to switch between different power supply states in a dynamically configurable way, without requiring external control over the configuration during switching.
    Type: Application
    Filed: May 22, 2015
    Publication date: November 19, 2015
    Inventors: Sasa Ristic, Insun Van Loo, Patrick E.G. Smeets
  • Patent number: 9052892
    Abstract: A power management integrated circuit comprises a plurality of power source circuits power received at a power supply input terminal to supply power to a plurality of power supply output terminals. A plurality of power source circuits is coupled between the power supply input terminal and the respective power supply output terminals. The power management integrated circuit comprises an active configuration memory and a communication interface with at least one terminal for uploading configuration data from outside the power management integrated circuit into the configuration memory. A control circuit controls operating parameters of respective ones of the power source circuits dependent on the configuration data from the active configuration memory. Thus, the power management integrated circuit is able to switch between different power supply states in a dynamically configurable way, without requiring external control over the configuration during switching.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: June 9, 2015
    Assignee: Ericsson Modems, SA
    Inventors: Sasa Ristic, InSun Van Loo, Patrick E. G. Smeets
  • Patent number: 7830293
    Abstract: Method and arrangement for cyclically AD converting an analog signal with a sampler capacitance and an integrator capacitance, comprising the steps of generating a difference signal multiplied by the ratio of said capacitances from the analog signal and a reference signal, deriving a digital bit from said difference signal, doubling the difference signal multiplied by said ratio, shifting said doubled signal by the reference signal multiplied by said ratio and using the shifted signal as difference signal multiplied by said ratio for the next cycle.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: November 9, 2010
    Assignee: NXP B.V.
    Inventors: Dimitrios Karavidas, Guillaume De Cremoux, Sasa Ristic, Yorgos Christoforou
  • Publication number: 20100250974
    Abstract: A power management integrated circuit comprises a plurality of power source circuits power received at a power supply input terminal to supply power to a plurality of power supply output terminals. A plurality of power source circuits is coupled between the power supply input terminal and the respective power supply output terminals. The power management integrated circuit comprises an active configuration memory and a communication interface with at least one terminal for uploading configuration data from outside the power management integrated circuit into the configuration memory. A control circuit controls operating parameters of respective ones of the power source circuits dependent on the configuration data from the active configuration memory. Thus, the power management integrated circuit is able to switch between different power supply states in a dynamically configurable way, without requiring external control over the configuration during switching.
    Type: Application
    Filed: May 27, 2008
    Publication date: September 30, 2010
    Inventors: Sasa Ristic, In Sun Van Loo, Patrick E. G. Smeets
  • Publication number: 20100201555
    Abstract: Method and arrangement for cyclically AD converting an analog signal with a sampler capacitance and an integrator capacitance, comprising the steps of generating a difference signal multiplied by the ratio of said capacitances from the analog signal and a reference signal, deriving a digital bit from said difference signal, doubling the difference signal multiplied by said ratio, shifting said doubled signal by the reference signal multiplied by said ratio and using the shifted signal as difference signal multiplied by said ratio for the next cycle.
    Type: Application
    Filed: June 8, 2005
    Publication date: August 12, 2010
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Dimitrios Karavidas, Guillaume De Cremoux, Sasa Ristic, Yorgos Christoforou